!!! IMPORTANT ANNOUNCEMENT !!!

Due to the coronavirus (COVID-19) pandemic, the ICMTS Steering Committee and 2020 Organising Committee have decided to have hold a virtual conference hosted online with the assistance of the IEEE, the opening of the conference is the 4th of May and it will be open for two weeks. Registration for the virtual conference will be open very soon and we will announce the confirmed dates for the conference to go online as soon as this is confirmed with IEEE.

Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration

The virtual conference will follow an asynchronous model, papers will be arranged into sessions as detailed below but the dates and timings given can be ignored. Attendees will be able to view papers and presentations in their own time and ask questions of the authors.

Day 1 - April 07

08:00 Registration
09:00 N/A
09:00 Session 1 1. Advanced measurement techniques
Co-Chairs: VERZI, Bill, Keysight, USA
09:00 [1-2] Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics
Shinichi Nishizawa and Kazuhito Ito
Extraction method of process variation is proposed. Process monitor circuits are widely used for the extraction of process variation, however adding special purpose circuit increase the silicon area. Usually, silicon chips are tested electrically and functionally after the fabrication. IDDQ test is an electrical test which measures leakage current and find the fault in the target chip. Scan-test is a functional test which inputs and measures the internal signal vector using scan- flip-flop. We propose to an extraction method of process variation utilizing IDDQ test and retention characteristics of scan-flip-flop. This method enables process variation extraction without any extra process monitor circuit. Test structures are implemented into silicon chips and result shows global variation shift is extracted as threshold voltage shift.
09:20 [1-3] Calibration of CBCM Measurement Hardware
Brad Smith, Emmanuel Onyegam, Donald Hall, and Bill Verzi
CBCM measurements require precise measurement of AC currents. This work describes a test structure that was used to demonstrate capability of test hardware to be used for that measurement. A series of inverters was used to create periodic spikes of current of three magnitudes and at a wide range of frequencies. Current measurements using a Keysight 4072 tester were completely linear with frequency across a four-decade frequency range, and for average currents as low as 530 pA. This technique could be used to validate the limits any test hardware prior to designing an AC circuit.
09:40 Coffee Break
10:10 Session 2 2. Parametric tests
Co-Chairs: DRIUSSI, Francesco, University of Udine - DPIA
10:10 [2-1] Extraction of Ultra-Low Contact Resistivity by End-Resistance Method
Bing-Yue Tsui, Ya-Hsin Lee, Dong-Ying Wu, Yao-Jen Lee, and Mei-Yi Li
The accuracy of extracting ultra-low contact resistivity (rho_c) by the end-resistance method is evaluated. As the contact length (Lc) becomes smaller than the transfer length (Lt), the endresistance (Re) approaches the contact resistance (Rc), and the error decreases with the reduction of Lc and rho_c. This end-resistance method is verified by self-aligned TLM test structure.
10:30 [2-2] Standardization of Specific Contact Resistivity Measurements using Transmission Line Method (TLM)
Sidhant Grover, Shubham Sahu, Peng Zhang, and Santosh K Kurinec
This study investigates the effect of TLM dimensions on the extracted values of specific contact resistivity rho_c. It is observed that the extracted rho_c depends on the TLM design, which varies for different applications. It is recommended that TLM dimensions be standardized for respective application used in structures, for example in ICs and solar cells.
10:50 [2-3] Automated Generation and Measurement of Parametric Test Structures
P. Sullivan, A. Tsiamis, S. Smith, A.J. Walton and J.G. Terry
This paper reports the development of a process control chip compiler that automates the design of test chips for an optical direct write exposure tool (ML3 DMO). In addition to taking full advantage of inbuilt features of the DMO tool, the system also generates the software to characterise the specified test structures and this is interfaced to an automatic prober (Karl Suss PA 200) and a HP4062 rack of instrumentation. It uses open-source software (Python) and in contrast to previously reported parametric compilers this system is the first one specifically designed for an optical maskless lithography system targeted at rapid prototyping of microsystems.
11:10 [2-4] Characterization of parametric mismatch attributable to plastic chip encapsulation
Hans Tuinhout, Andrei Damian and Adrie Zegers-van Duijnhoven
This paper discusses a test structure and associated high-precision characterization approach to study mechanical-stress-induced deterministic and random performance changes of semiconductor devices in plastic encapsulated chips. The results quantify effects of lead frame mounting, wire bonding and molding and demonstrate the positive effects of a stress buffer layer.
11:30 Lunch
13:00 Exhibitor Presentations
13:30 Session 3 3. Noise measurements
Co-Chairs: TERRY, Jonathan G., The University of Edinburgh, UK
13:30 [3-1] Area-Efficient and Bias-Flexible Inline Monitoring Structure for FastFast Characterization of RTN and Transistor Local Mismatch in Advanced Technologies
A. Jayakumar, N.Chan, L.Pirro, O. Zimmerhackl, M. Otto, T. Kleissner and J. Hoentscheland
13:50 [3-2] Test Structures for Noise Reduction of Fully Depletion-Silicon on Insulator p-Type Tunneling FET Using Channel Orientation
Hyun-Dong Song, Hyeong-Sub Song, Sunil Babu Eadi, Hyun-Woong Choi, Ga-Won Lee, and Hi-Deok Lee
In this paper, the channel orientation of TFET is focused. The Proposed test pattern involves rotating TFET in the layout step to change the direction of the channel. As a result, the subthreshold slope and oncurrent are improved. Especially, low-frequency noise of devised pattern at 10 Hz reduced by about 100 times than normal TFET. The reason for improvement could be due to the distance between the silicon atoms increased, the Coulomb force, which affects the tunneling of the carrier, decreases.
14:10 [3-3] Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning
Misaki Udo, Kensuke Murakami, A.K.M. Mahfuzul Islam and Hidetoshi Onodera
For the near- or sub-threshold region operation to achieve minimum energy, it is often ignored that dynamic tuning of voltage causes additional delay variability. In this paper, we raise a concern on the increased delay variability when dynamic tuning of back-gate voltage is employed. The mechanism of the increase of variability under dynamic tuning of supply voltage and back-gate voltage is explained. Using the measurement results, the impact of back-gate tuning on delay variability is demonstrated, which should be considered for reliable circuit operation.
14:30 [3-4] Low Frequency Noise Behavior in Resistive Memory Devices with Hf/HfO2 Stack
DC performance and low frequency noise (LFN) behavior were studied on Hf/HfO2-based bipolar RRAM test structure. The LFN power spectral densities in both LRS and HRS states follow the dependence, showing different slopes and magnitudes from LFN characteristics. This is attributed to the electron flowing path and the traps/defects.
14:50 Break
15:20 Session 4 4. MEMS devices characterization
Co-Chairs: SMITH, Brad, NXP, USA
15:20 [4-1] Automated Wafer-Level Characterisation of Electrochemical Test Structures for Wafer Scanning
I. Schmueser, L. Mackay, F. Moore, K. Doherty, J. P. Elliott, A.R. Mount, A. J. Walton, S. Smith, and J. G. Terry
This paper presents an automated system for the electrochemical characterisation of micro-scale test structures at the wafer level, with the objective to identify good wafers suitable for full characterisation and device packaging. The integration of the on-wafer characterisation enables a quality assessment of the devices prior to packaging ensuring the development of this technology minimises the packaging of faulty sensors. The prototype system integrates all the elements for automated on-wafer in-line characterisation of electrochemically based systems thereby confirming the suitability of this approach for implementation on commercial automated probers, which are generally available for parametric testing. The system’s capabilities are demonstrated on a three-electrode cell design typically employed in electrochemical sensing applications.
15:40 [4-2] Verification and Induction Method for Low Frequency Response-based Failure Modes in Acoustic MEMS
Gergely Hantos and Marc Desmulliez
In this paper we present a novel verification and induction method for low frequency response-based failure modes in MEMS microphones. Response of the device is captured before and after focus ion beam induced defect in the diaphragm of the microphone. The deviation in the response is correlated to analytical results.
16:00 [4-3] A Rapid, Reliable and Less-destructive On-chip Mass Measurement for 3D Composite Material Testing Microstructures
Gilgueng Hwang, Christophe David, Alisier Paris, Dominique Decanini, Ayako Mizushima, Yoshio Mita
We have demonstrated a rapid, reliable and less-destructive on-chip mass measurement method. It is based on AFM pick-measure-place micromanipulation using Van der Waals attraction and the mass measurement by resonant frequency shift. The measurement sensitivity revealed to be 25 Hz/pg and it could be promising to characterize MEMS with complex geometries and composite materials.
16:20 [4-4] Test structure and measurement system for characterising the electrochemical performance of nanoelectrode structures
I. Schmueser, E. O. Blair, Z. Isiksacan, Y. Li, D. K. Corrigan, A. A. Stokes, J. G. Terry, A.R. Mount and A. J. Walton
This paper presents a complete test structure and characterisation system for the evaluation of nanoelectrode technology, which integrates microfabricated nanoelectrodes, 3D printing and surface tension-confined microfluidics. This system exploits the inherent analytical advantages of nanoelectrodes that enables their operation with small volume samples, which has potential applications for on-wafer measurements.
16:40 End

Day 2 - April 08

08:30 Registration + Bonus Talk
08.30 Bonus Talk - Details To Be Confirmed
09:00 Session 5 5. Materials characterization
Co-Chairs: CAGLI, Carlo, CEA/LETI, France
09:00 [5-1] Multiscale modeling of charge transport properties and defect characterization of high-K bilayer CeO2/La2O3
Behnood Dianat, Paolo La Torraca, Yuri Ricci, Luca Larcher
Presence of defects in high-k gate dielectric materials such as cerium oxide and lanthanum oxide affects electrical properties of these materials. Hence, Intrinsic and defect characteristics of CeO2 and La2O3 were investigated. In this work a comprehensive charge transport model was used to study carrier conduction through the device. After defect characterization, it was found that neutral vacancies (V0) has the most contribution to electron/hole conduction. Trap energy levels for La2O3 and CeO2 are 2.1 and 1.7 eV below conduction-band respectively which agrees with other reports. Carrier conduction through traps are perfectly explained by trap-assisted-transport mechanism.
09:20 [5-2] Electrical and optical localisation of leakage current and breakdown point in SiOC:H low-k dielectrics
Matthias Vidal-Dhô, Quentin Hubert, Patrice Gonon, Bernard Pelissier, Philippe Lentrein, Patrice Ray, Jean-Michel Moragues, Pascal Fornara
This paper presents a study of a SiOC:H low-? dielectric material, in particular its emission properties under stress. A methodology is also proposed to localise electrically the material breakdown point after reliability tests. Our results show that leakage current increase is the result of a moisture-induced SiOC:H low-? dielectric material evolution throughout the whole structure.
09:40 [5-3] Simulation Marco-Model for Hf0.5Zr0.5O2-based Ferroelectric Capacitor
Jianjian Wang, Jinshun Bi, Hua Bai, Gang Liu, Kai Xi, Bo Li, Sandip Majumdar
A macro-model of ferroelectric capacitor for circuit simulation is established and extracted from the fabricated Hf0.5Zr0.5O2-based ferroelectric test structures. The macro-model is described by SPICE netlist and simulated by Hspice tools. Simulation results fit perfect with the P-V curves from the experimental measurement results, which proves high accuracy of the established model.
10:00 [5-4] OxRAM BER scaling trends on 4kb mixed-diameter test vehicle
J. Sandrini, C. Cagli, L. Grenoiullet, N. Castellani, V. Meli, F. Gaillard
We show a 4kb OxRAM test structure which includes devices of diameters ranging from 30nm to 170nm. This matrix allows to evaluate the impact of scaling over several performance metrics. We show that dual-bit cells allow a 10x BER reduction compared to single ones at the same area.
10:20 [5-5] Doughnut Test Structure to Evaluate ZnO/Si Heterostructure to Improve Efficiency of PbS QD/ZnO/Si Hybrid Infrared Photodiode
Norihiro Miyazawa, Naoto Usami, Haibin Wang, Takaya Kubo, Yoshio Mita, and Akio Higo
Hybrid infrared-sensitive optoelectronic device on silicon-based LSI is under investigation. In the last ICMTS, we have reported that heterojunction of PbS colloidal dots and ZnO nanowires over ITO electrode gave very high External Quantum Efficiency (EQE over 30% for 1300nm), but PbS-ZnO on our n-type Si substrate gave very low EQE (0.6%). To locate the cause of the low device efficiency, we applied doughnut-shape test structure to ZnO/Si interface. As a result, we found that ZnO/Si junction behaved like reverse-biased barrirer. Accordingly, the usefulness of employed test structure for investigating the heterojunction was confirmed.
10:40 Break
11:10 Session 6 6. MEMS Process characterization
Co-Chairs: MITA, Yoshio, U. Tokyo, Japan
SMITH, Stewart, U. Edinburgh, UK
11:10 [6-1] A nondestructive analysis method for the releasing process of thermal sensors
Chao Liu, Jianyu Fu, Ying Hou, Ruiwen Liu, Qiong Zhou, Dapeng Chen
Releasing process is a crucial technology to fabricate the suspended structure but easy to generate insufficient release and over release defects. We proposed a nondestructive analysis method to detect the releasing defects by analyzing their thermal parameters of thermal sensors. The analysis results are consistent with the SEM results for the different releasing morphologies.
11:30 [6-2] Drop-in test structure chip to visualize residual stress of Cu supercritical-fluids-deposition (SCFD)
Naoto Usami, Etsuko Ota, Akio Higo, Takeshi Momose and Yoshio Mita
We propose a drop-in test structure chip to evaluate residual stress in Cu film induced during supercritical fluid deposition (SCFD) process. Despite its importance, classical stress evaluation methods such as wafer curvature radius measurement is difficult to be applied to SCFD film because the sample chip size is small. We propose to “drop-in” a test chip on with free-standing MEMS test structure. It is thereby possible to extract information on reliability and reproductivity of SCFD without destroying the sample chip. A selective deposition on microcantilevers is utilized for stress visualization and revealed tensile-stress under the tested condition.
11:50 [6-3] Microheater isolation characterisation to aid the optimisation of a MEMS Leidenfrost engine
Anthony Buchoux, Prashant Agrawal, Gary G. Wells, Rodrigo Ledesma?Aguilar, Anthony J. Walton, Jonathan G. Terry, Glen McHale, Khellil Sefiane, and Adam A. Stokes
This paper reports on the implementation of test structures to characterise the design of a microheater that will allow localised heating to power Leidenfrost micro?engines. These structures involve etching trenches in a silicon substrate to enable characterisation of their effect on heat transfer. Initial results indicate that a trench just 218 ?m deep (less than half?way through the silicon substrate), results in the temperature in a region outside of the microheater device area being reduced by 3.6 ± 0.2 °C after being powered for 2 mins.
12:10 [6-4] Test structure for measuring etch selectivity in vapour etch processes
Markus Rondé, Anthony J. Walton, Jonathan G. Terry
Etch selectivity between layers is an extremely important concern in the fabrication of microelectronics and microsystems. This is particularly true in the case of vapour etching methods used to release free standing structures through the selective etching of sacrificial layers. Commonly used structural materials have been reported to be largely inert when exposed to a given vapour etchant, indicating high selectivity when measured against typical sacrificial layers. However, there is growing evidence that these structural layers are actually etched at an enhanced rate if they are located in the proximity of the sacrificial layer being removed. Hence, removal rates given in the literature that have resulted from measurements of layers that have been etched in isolation can no longer be trusted to characterise critical etch processes in device fabrication. In this paper, a test structure is reported that enables a far more accurate determination of the etch selectivity between sacrificial and structural materials.
12:30 Lunch
14:00 ICMTS 2021 Presentation + Invited Talk 2
14.00 - ICMTS 2021 Presentation 14.10 - Invited Talk 2
14:10 Invited Talk Invited Talk Session 2
Co-Chairs: SMITH, Stewart, U. Edinburgh, UK
14:10 [N/A] Keynote - Experimental Set-Up For Novel Energy Efficient Charge-based Resistive RAM (RRAM) Switching
P. Trotti, S. Oukassi, G. Pillonet, G. Molas, E. Nowak
This work explores a new method to reduce the energy consumption during the writing of process-spread resistive-based memories (RRAM), based on setting an initial electrical charge into a writing capacitor rather than applying constant voltage over a fixed time. By connecting a charged capacitor (constant charge source, CQS) to a RRAM device, we benefit of a lower energy requirement for setting the memory cells, for a given success rate. We derive a statistical RRAM compact model from experimental data, and benchmark our proposed writing procedure with respect to the constant voltage source (CVS) approach. Finally, we give experimental proof of concept by realization of a circuit interface that integrates the CQS protocol, connected to a RRAM load. Results support the fact that setting the initial charge is a better choice to control efficiently the variability of the filamentary process in RRAM.
Invited Talk 2 - To Be Confirmed
14:50 Session 7 7. RF Devices characterization
Co-Chairs: Colin McAndrew, NXP, USA
14:50 [7-1] Novel Statistical Modeling and Parameter Extraction Methodology of Cutoff Frequency for RF-MOSFETs
Chika Tanaka, Yasuhiko Iguchi, Atsushi Sueoka, and Sadayuki Yoshitomi
The cutoff frequency (fT) fluctuation in RF-MOSFET had been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of intrinsic parameter were performed. The global statistical fT model was successfully developed in terms of capacitance fluctuation, considering intrinsic and extrinsic components separately and identifying the major variability sources.
14:50 [7-2] Influence of series resistance on the experimental extraction of FinFET noise parameters
Angeliki Tataridou, Gerard Ghibaudo, Christoforos Theodorou
In this paper we demonstrate for the first time how the series resistance of a FinFET device can lead to an incorrect extraction of noise parameters, especially concerning the mobility fluctuations, correlated to the carrier number fluctuations. We also present an original method for suppressing this effect, by taking advantage of the series resistance immune Y-function.
14:50 [7-3] Comparison of nMOSFET Structures for Millimeter- Wave Frequencies in 0.18?m CMOS technology
Toyoyuki Hagiwara, Natsu Yamaki, Kyoya Takano, Yohtaro Umeda
We present two nMOSFET structures (A: compact-type B: round-table-type) with the high maximum oscillation frequency (fmax) in 1P5M 0.18-?m CMOS technology for millimeter-wave applications. By reducing their parasitics, we achieve the fmax of 95 GHz, which is approximately 2 times compared to that of the conventional structure reported in [1,2]
14:50 [7-4] Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events
Matt Lauderdale, Emmanuel Onyegam, Scott Ruth, Brad Smith and Alex Gerdemann
New wafer technologies and chip design requirements are increasingly susceptible to damage from smaller Electro Static Discharge events (ESD). A method is needed to evaluate ESD risk posed by processing equipment and the effectiveness of proposed upgrades. This paper proposes and investigates a packaged test structure designed to measure ESD events. The test chip would run in the place of production parts during equipment and package level process evaluations. A design is proposed, developed and preliminary test results demonstrating feasibility are shown. – Note: this paper was submitted for 2019 ICMTS; but, the final paper could not get legal clearance from NXP before the conference last year.
14:50 [7-5] Application of Broadband RF Metrology to Integrated Circuit Interconnect Reliability Analyses: Monitoring Copper Interconnect Corrosion in 3D-ICs
Papa K. Amoah, Jesus Perez, and Yaw S. Obeng
Certain commercial equipment, instruments, or materials are identified in this report in order to specify the experimental procedure adequately. Such identification is not intended to imply recommendation or endorsement by the National Institute of Standards and Technology, nor is it intended to imply that the materials or equipment identified are necessarily the best available for the purpose.
14:50 End of Day 2
Banquet will begin at 19.00

Day 3 - April 09

08:30 Registration
09:00 Session 8 8. MOSFET characterization
Co-Chairs: HABU, Satoshi, Keysight, Japan
09:00 [8-1] Anomalous scaling of parasitic capacitance in FETs with a high-K channel material
A.E.M. Smink, M.J. de Jong, H. Hilgenkamp, W.G. van der Wiel, and J. Schmitz
We investigate FET operation in devices of which the channel consists of a 2-dimensional electron system at the surface of a high-K channel material, SrTiO3 (K = 300). Our devices have low gate leakage and are the first of their kind with a sub-nm equivalent oxide thickness, which can only be properly determined after subtracting a parasitic capacitance that has an unusual 1/3-power dependence on the device length and width.
09:20 [8-2] Comparison of Extraction Methods for Threshold Voltage Shift in NBTI Characterization
Yu-Hsing Cheng, Michael Cook, Chris Kendrick
Extraction methods for threshold voltage shift in NBTI characterization were compared and evaluated for 3.3V PMOS devices in a 0.18?m process. The methodology in this work provides validation method of single ID measurement for fast determination of VT shift in NBTI to check if they are applicable for the specific process.
09:40 [8-3] Integrated Variability Measurements of 28nm FDSOI MOSFETs down to 4.2K for Cryogenic CMOS Applications
B. Cardoso Paz, L. Le Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. G. M. Jansen, S. Haendler, A. Juge, E. Vincent, P. Galy, G. Ghibaudo, M. Vinet, S. de Franceschi, T. Meunier and F. Gaillard
Mismatch performance of 28nm FDSOI technology is electrically characterized at low temperatures using integrated on-chip addressing for a matrix of transistors. The first statistical results ever published on FDSOI variability at 4.2K provide valuable information for future compact transistor modeling in cryogenic circuit design.
10:00 [8-4] Generalized Constant Current Method in Weak and Moderate Inversion for Determining MOSFET Threshold Voltage
Matthias Bucher, Nikolaos Makris and Loukas Chevas
A novel methodology for the extraction of threshold voltage and substrate effect parameters of MOSFETs biased in weak and moderate inversion is presented. This generalized constant-current method (GCCM) exploits the charge-based model of MOSFETs, and covers effects of edge conduction or subthreshold hump in MOSFETs using Shallow Trench Isolation (STI).
10:20 Break
10:50 Session 9 9. Optoelectronic devices characterization
Co-Chairs: WEILAND, Larg, PDF, USA
10:50 [9-1] Comparison of cut-back method and optical backscatter reflectometry for wafer level waveguide characterization
Anna Peczek, Christian Mai, Georg Winzer and Lars Zimmermann
The optimum optical characterization method suitable for wafer level waveguide testing is an important issue for silicon photonic methodology. In this paper we focus on comparing the two most widespread measurement techniques: cut-back and optical backscatter reflectometry. Wafer level test results are compared for different types of waveguides.
11:10 [9-2] Diode design for studying material defect distributions with avalanche-mode light emission
M. Krakers, T. Knezevic, K.M. Batenburg, X. Liu, L.K. Nanver
Avalanche-mode visual light emission in Si diodes is shown to be useful for rapid assessment of the origin of non-ideal currents. In the test structure design it was important to consider the breakdown-voltage distribution, diode size and contact positioning to obtain light-spot appearances at positions related to bulk defect distributions.
11:30 [9-3] Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo{Diodes
F. Driussi, A. Pilotto, D. De Belli, M. Antonelli, F. Arfelli, G. Biasiol, G. Cautero, R. H. Menk, C. Nichetti, L. Selmi, T. Steinhartova, P. Palestri
Extensive experimental characterization and TCAD simulation analysis have been used to study the dark current in Avalanche Photo{Diodes (APDs). The comparison between the temperature dependence of measurements and simulations points out that SRH generation/recombination is responsible for the observed dark current. After the extraction of the carrier lifetimes in the GaAs layers, they have been used to predict the APD collection eciency of the photo{generated currents, that is of about 55% under realistic operation conditions.
11:50 [9-4] Test Setup Optimization and Automation for Accurate Silicon Photonic Wafer Acceptance Production Tests
Choon Beng Sia, Tiong Leh Yap, Ashesh Sasidharan, Jun Hao Tan, Robin Chen, Jacobus Leo, Soon Leng Tan and Guo Chang Man
Implementing energy-efficient optical transceivers with silicon photonics (SiPh) technology for hyperscale data centers will help alleviate the increasing energy demand, expected to be 20% of earth’s total energy output by 2030. To facilitate SiPh wafer acceptance tests, this paper proposes methods to optimize and implement a fully automatic SiPh wafer test architecture.
12:10 Closing Remarks
Including Best Paper Announcement
12:30 End