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Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Day 1 - March 22

08:00 Registration
09:00 Welcome
09:10 Session 1 Process Characterization I
Co-Chairs: VERZI, Bill,
09:10 [1-1] Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization
Misaki Udo, Mahfuzul Islam and Hidetoshi Onodera
Ring oscillator circuits are useful for the character- ization of MOS transistors under switching operation. Accurate characterization of per-gate variation becomes difficult when the ring oscillator consists of many stages or has heterogeneity. We propose a homogeneous ring oscillator structure with a staggered layout. Using a header transistor instead of a NAND for oscillation control, our proposed structure can realize a 3- stage RO where the three stages have equal delay contributions. By measuring the test chip, we demonstrate the validity of the proposed structure for gate-level characterization.
09:30 [1-2] Test Structures for Characterising Spatial Proximity Effects in the Fabrication of Electrochemical Sensors
09:50 [1-3] Design of Low-Cost Test Structures for Measuring Within-Die Process Skew Variations
Amitava Majumdar and Nui Chong
The potential for expanding the use of ring oscillators (ROs) into a new and, as yet, unexplored area was reported in [1]. Simply stated, departures in strengths of PMOS and NMOS transistors from nominal, cause changes in duty- cycles at different nodes of ROs. Given the right RO design, both DC & AC behavior of transistors in process-skew can be determined at the same time. In this paper we address the related engineering problem of creating such RO designs that are specifically tuned for sensing process-skew. Design criteria and methodology are defined for ROs that are sensitive to and, in some sense, amplify process- skew. The simplicity of proposed designs allows distributing many instances of these sensors on a die, in turn, creating the possibility of characterizing within-die process skew variations.
10:10 [1-4] Combined Machine Learning Techniques Based Automatic Pass/Fail Checks on Transistor Characteristics
Hüsnü Murat Koçak Jerome Mitard Ahmet Teoman Naskali
We present a multi-model ensemble, composed of Convolutional Neural Networks (CNNs) approach to enable fast classification of transistor characteristics, combined with Machine Learning (ML) model to extract key parameters that allow us to measure the performance of ultra-scaled devices. Our current CNN-based approach has demonstrated accuracy above %90 with an execution time significantly faster compared to cur- rent human expert based methods. The proposed CNN technique which does not incorporate hard coded domain knowledge, is also tested with input data coming from widen-spread 16nm- node FinFET technology and evaluated by experts to prove the universality of the model using the same parameters
10:30 Break
10:50 Session 2 RF
Co-Chairs: JEPPSON, Kjell, Chalmers U, Sweden
10:50 [2-1] S-parameter Measurement and EM simulation of Electronic Devices towards THz frequency range
Chandan Yadav, Sebastien Fregonese, Marina Deng, Marco Cabbia, Magali De Matos,Thomas Zimmer
In this paper, we present on-wafer S-parameter measurement and EM simulation analysis of silicon-based devices up to 750GHz. The on-wafer TRL calibrated S-parameter measurement is shown up to 500 GHz along with the intrinsic EM simulation (ideal behavior). An EM model of an RF probe is designed to analyze on- wafer S-parameter measurement of silicon devices above 500 GHz. The differences between the intrinsic EM simulation and simulation with RF probe model shows challenges in accurate on-wafer S-parameter measurement of silicon devices in sub-THz and THz range.
11:10 [2-2] 300-GHz Back-Radiation On-Chip-Antenna Measurement with Electromagnetic-Wave-Absorption Sheet
Sangyeop Lee, Kosuke Katayama, Kyoya Takano, Masao Fujita, Masayuki Toyoda, Shinsuke Hara, Issei Watanabe, Akifumi Kasamatsu, Shuhei Amakawa, Takeshi Yoshida, and Minoru Fujishima
A method using a 300-GHz electromagnetic-wave-absorption sheet to improve measurement accuracy for a back-radiation on-chip antenna is demonstrated. Electromagnetic-wave reflection owing to the material beneath a chip substrate occurs during the on-wafer measurement, leading to the input-impedance variance of that antenna at the feeding port.
11:30 [2-3] Modeling and Verification of Millimeter-Wave nMOSFET up to 50 GHz in 180 nm CMOS Technology
Koki Sekine, Kyoya Takano, and Yohtaro Umeda
We present the modeling method of an nMOSFET up to 50 GHz fabricated in the 180 nm CMOS process, and verify it using a 20 GHz oscillator with the second harmonic of 40 GHz. We show that the difference between the simulated and measured oscillation frequencies is below 5 %.
11:50 [2-4] Optimal test structures for the characterization of integrated transformers at mm-wave frequencies using the open/thru de-embedding technique
Mario Lauritano and Peter Baumgartner
This article investigates the characterization of integrated transformers at mm-wave frequencies using the open/thru de-embedding methodology. Using electromagnetic simulations some layout guidelines for the test fixture are derived which allow to obtain good accuracy in spite of the simple method. A testchip with several test structures implementing these guidelines is fabricated and measured to demonstrate the concept.
12:10 Lunch
13:30 Invited Talk 1
14:00 Session 3 Reliability
Co-Chairs: LEE, Hi-Deok, Chungnam NU, Korea
14:00 [3-1] Two-pads per electrode in-situ test structure for micron-scale flip-chip bonding reliability of chip-on-chip device
Yusuke Ebihara, Ayako Mizushima, Takashi Yoda , Kenji Hirakawa, Masayuki Iwase, Munehiro Ogasawara, Akio Higo, Yukinori Ochiai, and Yoshio Mita
Arrayed CMOS-MEMS Devices are often made separately, and they are face-to-face flip-chip bonded for electrical connection. We propose an in-situ testing method by ”two-pad-per-electrode” design to check the contact of bonding pads, which enables testing bonding contact between production chips and identification of the place of defects.
14:20 [3-2] Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures
A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez, F.V. Fernandez
Summary: This work presents an IC array with custom test structures for the characterization of TDV phenomena that includes three types of circuits: inverters, single-stage amplifiers, and current mirrors. The array allows the characterization of these circuit blocks through a wide variety of metrics and different stress and operating conditions.
14:40 [3-3] Utilization of Poly Heater Test Structures in NBTI Characterization
Yu-Hsing Cheng, Michael Cook, Derryl Allman
Test structures with a poly heater and a dedicated diode were employed in NBTI characterization for 5V PMOS devices in a 0.18?m CMOS smart power technology to utilize in situ temperature changes with results in good agreement with data from fast measurement system. This test methodology provides a tool for fast NBTI assessment of wafer level reliability.
15:00 Break
15:20 Exhibitor Presentation
15:50 Session 4 Process Characterization II
Co-Chairs: WEILAND, Larg, PDF, USA
15:50 [4-1] Layout-Dependent Vertical and In-Plane Leakage Current Reduction of Organic Thin-Film Transistors by Layer-Contact Restriction
Kunihiro Oshima, Kazunori Kuribara, and Takashi Sato
We evaluate and reduce layout-dependent leakage currents of organic thin-film transistors (OTFTs). Measurement results show that no-protrusion source-drain layout over gate-metal and semiconductor reduces leakage currents, improving the pull-down voltage level of OTFT logic gates for achieving rail-to-rail operation.
16:10 [4-2] Temperature Characterizations of Multi-Unit and Multi-finger Dependencies on AlGaN/GaN Ridge HEMTs
Hitoshi Aoki, Naotaka Kuroda, Atsushi Yamaguchi, and Ken Nakahara
Temperature and geometry dependencies on drain current including hole injection current, self-heating, and current collapse by buffer potential of AlGaN/GaN ridge HEMTS (known as gate injection transistors) have been characterized with our dedicated test structures including multi-finger and multi-unit devices in addition to the gate length and width variations.
16:30 [4-3] Single Device MOSFET Series Resistance Extraction Methods: Comparison Between Newer and Older
Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto
Recently, the present authors proposed a series resistance ( R SD ) extraction method using multiple I D vs. V G curves at different drain biases of a single MOSFET. The method takes into account both V G and V D dependence of mobility in an intuitive manner using a convergence of curves concept. This presentation will compare this method with an earlier one, by which the authors were inspired, using TCAD simulations. Advantages of the newer method will be illustrated.
16:50 close
17:30 Happy Hour

Day 2 - March 23

08:00 Registration
09:00 Session 5 Memory
Co-Chairs: CAGLI, Carlo, CEA/LETI, France
09:00 [5-1] Embedded measurement of the SET switching time of RRAM memory cells
F.Jebali, E. Muhr, M. Alayan, M.C. Faye, D. Querlioz, F. Andrieu, E. Vianello, G. Molas, M. Bocquet, J.M. Portal
This paper presents an embedded measurement circuit dedicated to the extraction of the SET switching time of RRAM memory cells. A brief overview of the measurement circuit, designed in a hybrid 130nm technology with HfO2 BEoL RRAMs, is given with emphasis on the write termination (WT) mechanism and the switching time acquisition thanks to a Time-to-Digital Converter (TDC) shift and capture mechanism. Test conditions are then described, together with the measured RRAM resistance values and the associated SET switching times. Resistances and SET switching time values fully complies with the ones obtained in the literature through a heavy waveguide measurement setup, validating our approach.
09:20 [5-2] Statistical Modeling of SRAM PUF Cell Mismatch Shift Distribution After Hot Carrier Injection Burn-In
Kunyang Liu, Kiyoshi Takeuchi, and Hirofumi Shinohara
This manuscript presents statistical modeling for the PUF cell mismatch shift with respect to HCI burn-in, using the compound distribution based on a Poisson distribution and a Gamma distribution. The model matches the experimental result collected from 130-nm CMOS test chips.
09:40 [5-3] SuperCAST: a full free adressable memory array
Vincenzo Della Marca, Julien Guilleau-Tavernier, Pierre Laine, Franck Melul , Marc Bocquet, Thibault Kempf, Loic Welter, Jean-Michel Moragues, Arnaud Regnier and Jean-Michel Portal
We present a full free addressable 4kb EEPROM memory array. This structure based on CAST vehicle has been upgraded with column/row shift registers to enable easy bit selection implementation in an embedded non-volatile memory environment. High voltage circuits allow to perform electrical characterizations and reliability test for in-memory computing applications.
10:00 [5-4] CMOS Platform TEG for Development of High Performance Synaptic Devices
Yeong-Jin An, Seong-Hyun Kim, Ki-Woo Song, Hyun-Jin Shin, Tae-Gyu Ryu, Sunil-Babu Eadi, Hyuk-Min Kwon, and Hi-Deok Lee
In this paper, our team designed complementary metal–oxide–semiconductor(CMOS) platform test element groups(TEGs) to evaluate the main characteristics of synaptic devices, i.e., variability, reliability, and applicability to neuromorphic chips. We demonstrated the performance and the application of the TEGs by integrating and measuring memristors on these TEGs.
10:20 Break
10:50 Session 6 Materials Characterization
Co-Chairs: YOUNG, Chadwin, University of Texas at Dallas
10:50 [6-1] An Evaluation for Quality Inspection of Epitaxial Layer and Heavily-doped 4H-SiC Substrate by Simple Schottky Barrier Diode and MOS Capacitor
Kuan-Wei Chu, Chun-Wei Tseng, Bing-Yue Tsui, Yew-Chung Sermon Wu, Cheng-Juei Yang and Chuck Hsu
11:10 [6-2] Application of a Test Structure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films
A.W.S. Ross, C.W. Dover, S. Smith, J.G. Terry, A.R. Mount, and A.J. Walton
This paper presents a previously documented full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. With magnetic films, non-magnetic seed layers need to be as thin as possible to minimise unwanted eddy currents. This paper uses the test structure to quantify the IR drop on the electroplated film and demonstrates how current distribution structures can be simply used to significantly improve wafer plating uniformity when using seed layer thicknesses of a few nanometers.
11:30 [6-3] Test Measurements for Differentiating Polarization Switching from Charge Trapping in Ferroelectric FETs
Shan Deng, Kai Ni, and Santosh Kurinec
This study presents a measurement methodology to separate the effects of ferroelectric polarization switching from charge trapping and de-trapping effects in Ferroelectric Field Effect Transistors (FeFETs). Combining the write pulse and transfer characteristics read for memory window measurement with one-spot measurement demonstrates the interplay between the polarization switching and charge trapping effects.
11:50 Lunch
13:10 Invited Talk 2
13:40 Session 7 Yield
Co-Chairs: RERECICH, Matt, Samsung, Austin
13:40 [7-1] DFI Filler Cells – New Embedded Type of Test Structures for Non-Contact Detection of Electrical Defects on Product Wafers
Stephen Lam, Christopher Hess, Larg Weiland, Matthew Moe, Xumin (William) Shen, John Chen, Indranil De, Marcin Strojwas, Tomasz Brozek
A new type of test structures has been developed for process monitoring and defect detection on product wafers. The structures are part of the Design-for-Inspection (DFI) platform. They are electrically tested in a non-contact way using a dedicated and specially optimized eBeam tool. They are designed to be compatible with standard cells and to be used as filler cells in standard cell-based logic designs. The paper will present the design and usage of such DFI structures as well as illustrated results collected from scanning product wafers containing embedded DFI filler cells.
14:00 [7-2] Contact Fail Monitoring with an Epi Resistance Test Structure for 7nm FinFET Product
C.H. Lee, K. Onishi, C. Manya, S. Wu, L. Anastos, J. Sim, M. Angyal
This paper describes a test site and yield issues in FinFET product.
14:20 Break
14:40 ICMTS 2023
14:50 Session 8 Test
Co-Chairs: RERECICH, Matt, Samsung, Austin
14:50 [8-1] Issues and advances in rapid Quasi-Static CV for high throughput semiconductor process monitoring
Michael H. Herman, Adrianna Galletta, Daniel Jang, Mark Nagel, Ben Morris
A rapid Quasi-Static Capacitance-Voltage (QSCV) method has been advanced to produce simultaneous Cp and Rp values. Multi-segment voltage stimulus waveforms generate digitized currents from single or parallel DUTs. Resulting current vectors are resolved into Rparallel (Rp) and Cparallel (Cp) values. We compare QSCV and LCR methods and discuss instrument and modeling issues.
15:10 [8-2] Procedure for Controlling Pad Scrub During High-Temperature Wafer Probing
Donald Hall, Brad Smith, Dan Pechonis, Mike Nelson, and Garrett Tranquillo
Stability and control of high-temperature wafer probing was studied. A new procedure was demonstrated that enables control of the probe needle scrub distance at elevated temperatures. Initial scrub measurements were made and compared for three probe card motherboards at 125, 150, and 175 C. Then, applying the new procedure, scrub distance was measured at 175 C for the three motherboards over 144 hrs of probing. The new procedure enabled control (and thus, minimization) of the probe pad scrub distances.
15:30 Break
15:50 Session 9 Device Characterization
Co-Chairs: MORI, Takayuki, KanazawaI.T.
15:50 [9-1] dGPLVM: A Nonparametric Device Model for Statistical Circuit Simulation
Kyohei Shimozato, and Takashi Sato
A novel statistical device model, dGPLVM, is proposed in which device variation is compactly represented using low dimensional latent variables. The fitting accuracy of the dGPLVM and the generated device characteris- tics through the sampling in the latent space are validated using the measurement results of commercial power MOSFETs.
16:10 [9-2] Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers
J. van Zoeren, L.K. Nanver
Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Two different biasing schemes are examined for contacting adjacent diodes. Parasitic series resistance and/or lateral currents become limiting factors for diodes with high electron-to-hole current-ratios.
16:30 [9-3] Characterization and Monitoring Platform for Single-Photon Avalanche Diodes in the Development of a Photon-to-Digital Converter Technology
Samuel Parent, Frédéric Vachon, Valérie Gauthier, Jacob Deschamps, Tommy Rossignol, Philippe Arsenault, Caroline Paulin, Henri Dautet, Serge A. Charlebois, and Jean-François Pratte, Maxime Côté, Denis Dupont, Stéphane Martel
This paper reports on a wafer-level test platform for single-photon avalanche diodes (SPADs) manufactured at Teledyne DALSA (Canada) and designed by Université de Sherbrooke. The platform enables in-foundry end-of-process active testing of SPADs in Geiger-mode, thanks to a dedicated ASIC and probe card installed on a wafer prober.
16:50 Close
19:00 Banquet
21:00 Post Banquet
21:00 End of 2nd day

Day 3 - March 24

08:00 Registration
09:00 Session 10 Novel Device Characterization
Co-Chairs: SMITH, Stewart, U. Edinburgh, UK
09:00 [10-1] Test Structure of Bi-stable Spring towards TopoMEMS Ising Machine
Yoshio Mita, Motohiko Ezawa, Keigo Tsuji, Eric Lebrasseur, Tomoki Sawamura, Shinji Tsuboi, Ayako Mizushima, Yukinori Ochiai and Akio Higo
For future quantum annealing computer, Ising Model is drawing attention in recent years. We are investigating the World's first Topological Micro Electro Mechanical Systems (TopoMEMS) representation of Ising Model. As the core component, we propose a unique “compression-before-use” bi-stable spring structure. Two key parameters identified were initial gap and stress relief structure. fabricated, and parametrically tested. It was experimentally found that there exists a design window to realize 70um-stroke bi-stable operation with application voltage as low as 9V.
09:20 [10-2] A two-step parameter extraction methodology for graphene field-effect transistors
Kjell Jeppson
Accurate device models and parameter extraction methods are of utmost importance for characterizing graphene field-effect transistors (GFETs) and for predicting their performance in circuit applications. For DC characterization, accurate extraction of the GFET transconductance parameter (i.e. mobility) and series resistance is of particular concern. In this paper, extraction of these parameters will be reviewed. A first-order mobility degradation model that can be used to separate information about mobility degradation and series resistance for a set of GFETs will also be discussed.
09:40 [10-3] On-Chip Nano Pulse Test Element Group for Analysis of Synaptic Devices
Seong-Hyun Kim , Ki-Woo Song, Hyun-Jin Shin, Yeong-Jin An, Tae-Gyu Ryu, Sunil-Babu Eadi, Hyuk-Min Kwon, and Hi-Deok Lee
This paper proposes a On-Chip Nano Pulse test element group (TEG) for the long term potentiation/depression of synaptic devices, which can generate and apply the pulses to a synaptic device with multiple-ns widths in the wafer. The sampling measurement can also be performed because the pulse period can be changed.
10:00 [10-4] Introduction of a Reset MOSFET to Mitigate the Influence of Ionic Movement in Perovskite MOSFET Photodetector Measurements
Jinbo Liu, Ross Haroldson, Grigorii Verkhogliadov, Dayang Lin, Qing Gu, Anvar A Zakhidov, Walter Hu, Chadwin D Young
A Reset MOSFET is added to a perovskite MOSFET-based photodetector to serve as a current source to mitigate the influence of ionic movement on the performance of the photodetector. With the added MOSFET, the hysteresis is significantly reduced, and the dark current is controllable. The on/off ratio resumes to 10 6 and an ultrasensitive responsivity (over 80, 000 A/W) is achieved under only 13 nW/cm 2 red (665 nm) light intensity.
10:20 Break
10:50 Best Paper Award
10:55 Closing Remarks
11:00 Lunch
12:20 Excursion
12:20 End of 3rd day