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Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Day 1 - March 20

08:00 Registration
09:00 Welcome
09:10 Session 1 Process Characterization
09:10 [1-2] Test Structures for Debugging Variation of Critical Devices Caused by Layout-Dependent Effects in FinFETs
Qi Lin, Hans Pan, Jonathan Chang
We developed a set of test structures for monitoring and debugging the variation of critical devices caused by layout-dependent effects. These test structures were verified in 16nm FinFET technology. We also present two case studies of debugging FinFET device variation by using these test structures.
09:30 [1-3] Passive Permutation Multiplexer To Detect Hard and Soft Open Fails on Short Flow Characterization Vehicle Test Chips
Christopher Hess, Shia Yu
Short flow characterization vehicle test chips are a major contributor to fast learning cycles especially for BEOL process steps. While hard open fails can be easily detected even in large via chains, it is very difficult to detect soft open fails like a 100 times larger via resistance of just one via within a large chain of vias. A Passive Permutation Multiplexer (PPM) is presented to optimize the signal to noise ratio for detecting soft open fails. The PPM implements a balanced routing access to a local population of resistive Devices Under Test (DUT) such as via or contact chains. Thus, soft open fail are easily recognizable as outliers of all measured resistance values within such a local population of DUTs. Compared to traditional passive multiplexers, the PPM contains up to twice as many DUTs. Furthermore, significantly larger Design of Experiments (DOEs) can be implemented, since the PPM can hold more than just one DOE level within the same array.
09:50 [1-4] Novel test structures for extracting interface state density of advanced CMOSFETs using optical charge pumping
Hyeong-Sub Song, Dong-Jun Oh, So-Yeong Kim, Sung-Kyu Kwon, Sungju Choi, Dae Hwan Kim, Dong-Hwan Lim, Chang-Hwan Choi, Dong Myong Kim, and Hi-Deok Lee
In this paper, we proposed novel test structures to evaluate the distribution of interface state density of MOSFETs by using optical charge pumping method. Unlike other measurement methods to extract interface state density(Dit), which have a limited range of measurable energy states and influenced by gate area and gate leakage, Dit can be extracted without these problems by using the proposed test structures. Test structures were fabricated using a 0.18ìm CMOS process or FD-SOI technology with high-k dielectric, respectively. Optical charge pumping was performed in proposed test structures and Dit is extracted from 109 cm-2· eV-1 to 1013 cm-2· eV-1.
10:10 [1-5] Test Structure to Evaluate the Impact of Parasitic Edge Channel Current Behavior on Precision Analog Circuits
Dale McQuirk, Chris Baker, and Brad Smith
Parasitic edge FET effects on DGO NMOS devices operating in the sub-threshold region were studied using several test structures that emulate typical functions within analog circuits. An experiment was planned to implement a processing method experiment for reducing parasitic effects within the test structures. Results from one method demonstrated a significant reduction of parasitic edge effect.
10:30 Break
11:00 Session 2 Modeling & Parameter Extraction
11:00 [2-1] Comprehensive Investigation on Parameter Extraction Methodology for Short Channel amorphous InGaZnO ThinInGaZnO Thin-Film Transistors
Chika Tanaka and Keiji Ikeda
We proposed the comprehensive parameter extraction method for short channel amorphous InGaZnO (.-InGaZnO) thin-film transistors (TFTs) on the basis of measurement data and TCAD simulations. Single parameter set were successfully extracted for channel length down to 500nm by using RPI .-Si TFT model with channel length modulation modeling. It makes possible to more accurate and scalable circuit performance characterization, since the extracted parameters correspond to the physical behavior of .-InGaZnO TFTs.
11:20 [2-2] Modeling Split-Gate Flash Memory Cell for Advanced Neuromorphic Computing
Mandana Tadayoni, Santosh Hariharan, Steven Lemke, Thibaut Pate-Cazal, Bernard Bertello, Vipin Tiwari, and Nhan Do
Split-gate flash memory technology had recently been used in neuromorphic computation where a non-volatile memory array is designed in such a way that enables high-precision tuning of individual memory elements. This work proposes for the first time a SPICE model of the 2-transistor, select gate and floating gate, of the split-gate flash memory cell, implemented in a 180nm CMOS technology, that allows the users to set the individual memory cell to any precise analog state.
11:40 [2-3] Validation of the BSIM4 Irregular LOD SPICE Model by Characterization of Various Irregular LOD Test Structures
Bob Peddenpohl, Max Otrokov, Jeremy Wells
This paper shows the measurements results of Various Irregular LOD structures, and compares those measurements to the BSIM4 LOD model. The BSIM4 model takes an average of the stress along the FET width, and these measurements confirm the BSIM4 model predictions are reasonably accurate.
12:00 [2-4] Efficient Parameter-Extraction of SPICE Compact Model Through Automatic Differentiation
Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
A novel method for the extraction of MOSFET compact model parameters is proposed. The proposed method exploits automatic differentiation technique, utilized in backpropation to learn the parameters of arti cial neural network. In the automatic differentiation, gradient of all parameters of the MOSFET model is calculated with the reduced computational cost. On the basis of the calculated gradient, the model parameters are efficiently optimized. Through experiments using a SPICE model for SiC power MOSFETs, the proposed method achieved a 12.3x speedup compared to the numerical-differentiation method. In addition, it is demonstrated that the parameter extraction is accurately and effectively conducted in combination with a conventional metaheuristic algorithm based parameter extraction and proposed method.
12:20 Lunch
13:40 Invited Talk
14:10 Session 3 Reliability
14:10 [3-1] Test Structure Design for Model-Based Electromigration
Ertugrul Demircan, Mehul D. Shroff, and Hsun-Cheng Lee
As VLSI technology features are pushed to the limit with every generation and with the introduction of new materials and increased current densities to satisfy performance demands, failure risk due to Electromigraton (EM) is ever-increasing. In this paper, we present experimental results using a novel set of test structures to validate a new model-based EM risk assessment approach. In this method, EM risk can be assessed for any interconnect geometry through an exact solution of the fundamental stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily as we demonstrate on real design examples.
14:30 [3-2] ESD Test Structures for TLP and HBM Testing at Wafer Level
R. Ashton, S. Fairbanks, A. Bergen, and E. Grund
New two pin ESD testers are capable of doing both Transmission Line Pulse (TLP) and Human Body Model (HBM) testing at wafer level. These systems facilitate using test structures to link fundamental circuit element parameters measured with TLP and expected HBM results on final products
14:50 Exhibitors, Break
15:40 Session 4 Materials Characterization
15:40 [4-1] Reliability analysis of the metal{graphene contact resistance extracted through the Transfer Length Method
Stefano Venica , Francesco Driussi , Amit Gahoiy, Satender Katariay, Pierpaolo Palestri , Max C. Lemmeyz and Luca Selmi
Transfer Length Method is a well{established characterization technique for contact resistance in semiconductors; however, its dependability is questioned for metal{graphene contacts. We investigate in{depth the statistical error on the extracted contact resistance values and we devise strategies to limit such error and to determine reliable results.
16:00 [4-2] Test Structures for Seed Layer Optimisation of Electroplated Ferromagnetic Films
C.M. Mackenzie Dover, A.W.S. Ross, S. Smith, J.G. Terry, A.R. Mount and A.J. Walton
This paper presents test structures to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. The test structures enable the effect of IR drop on the electroplated film to be extracted and provides increased understanding to help optimise the seed layer thickness.
16:20 [4-3] Test structures without metal contacts for DC measurement of 2D-materials deposited on silicon
L. K. Nanver, X. Liu, and T. Knezevic
A set of ring-shaped test structures is presented for electrical characterization of as-deposited layers on Si that electrically interact with the substrate. The test method is illustrated by investigation of 3 different nm-thin layers that are expected to form an interfacial layer of negative fixed charge. A test procedure is described that gives a low turnaround time and non-destructive way of evaluating different deposition methods for 2D-type layers in terms of diode characteristics, interface conductance, and minority carrier injection into the deposited layer.
16:40 [4-4] Test structures for evaluating Al2O3 dielectrics for graphene field effect transistors on flexible substrates
Xinxin Yang, Marlene Bonmann, Andrei Vorobiev, Kjell Jeppson, and Jan Stake
17:00 [4-5] Design of Ultraflexible Organic Differential Amplifer Circuits for Wearable Sensor Technologies
Masaya Kondo, Takafumi Uemura, Mihoko Akiyama, Naoko Namba, Masahiro Sugiyama, Yuki Noda, Teppei Araki, Shusuke Yoshimoto, Tsuyoshi Sekitani
We have designed ultraflexible organic differential amplifier circuits for wearable sensor technologies. Transistor modelings for both p- and n-type organic thin-film transistors are prepared for circuit simulations. Developed organic amplifier shows high gain of 60 dB and operates with 3 V, which realizes imperceptible sensor circuits for biomedical applications.
17:20 End

Day 2 - March 21

08:00 Registration
09:00 Session 5 Mismatch & Variability
09:00 [5-1] A test structure to reveal short-range correlation effects of mismatch fluctuations in backend metal fringe capacitors
Hans Tuinhout, Adrie Zegers-van Duijnhoven and Ihor Brunets
This paper presents a set of DUT-1-2-1-2 capacitor matching characterization test structures that revealed a thus far unknown (at least unreported) CMP-related short-range correlated mismatch fluctuation mechanism, explaining the area scaling behavior of matching of backend metal fringe capacitors.
09:20 [5-2] Monte Carlo Analysis by Direct Measurement using Vth-shiftable SRAM Cell TEG
Shogo Yamaguchi, Daisuke Nishikata, Hitoshi Imi, and Kazuyuki Nakamura
The measurement system in which the Monte Carlo analysis of SRAM operation can be performed in actual measurement was developed. The measured results of the Monte Carlo analysis for SRAM function test and the static noise margin evaluation were agreed well with the simulated results. The proposed method can compactly cope with the recently proposed SRAM with a larger number of transistors.
09:40 [5-3] Process Variation Estimation using A Combination of Ring Oscillator Delay and FlipFlop Retention Characteristics
Takuma Konno, Shinichi Nishizawa, and Kazuhito Ito
We propose an extraction method of process variation. Extracted process variation is modeled as threshold voltage variation. Retention characteristic of a DFF circuit has different sensitivity to threshold voltage variation from a RO circuit. We propose to introduce a DFF circuit a complement test structure for standard RO circuit for process variation extraction. Combining RO and DFF circuits enables an accurate estimation of global process variation shift. Test structures are implemented into silicon chips and result shows global variation shift is extracted from measured data.
10:00 [5-4] NPN Mismatch Dependence on Layout
Cory Compton
Mismatch structures are normally designed to look at pairs of identical devices with near ideal layouts. In this paper we look into the effects of orientation and NPN density on the mismatch results of NPNs in a 0.18um SiGe BiCMOS process. The mismatch structures were added to scribeline PCM modules, which allows us to look at the results from multiple mask sets.
10:20 Break
10:50 Session 6 On-Chip Characterization
10:50 [6-1] On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation
Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
This paper proposes a monitor circuit that can estimate process variation and temperature by circuit reconfiguration. The circuit topology of the temperature monitoring is crafted such that the oscillation frequency is determined by the amount of leakage current which has an exponential dependency to temperature. The voltage dependence of this circuit is small in the configuration for temperature measurement, and the temperature dependence is small in the configuration for process variation estimation. A test chip structure fabricated in a 65 nm CMOS process demonstrates the temperature estimation capability with accuracy within -0.3 C to 0.4 C over a temperature range of 10 C to 100 C, as well as the ability for estimating threshold voltage variations.
11:10 [6-2] DFT-enabled Within-die AC Uniformity and Performance Monitor Structure for Advanced Process
Nui Chong, I-Ru Chen, Da Cheng, Amitava Majumdar, Ping-Chin Yeh, Jonathan Chang
An on-chip ring oscillator based monitoring vehicle embedded within host blocks and accessed through DFT circuit is introduced and characterized. Within-wafer AC uniformity, performance and power are analyzed in a 7nm testchip. The design and analysis techniques described are suitable to monitor process variation, real-time power fluctuation and product performance.
11:30 [6-3] Versatile Chip-level Integrated Test Vehicle for Dynamic Thermal Evaluation
Suresh Parameswaran, Saravanan Balakrishnan, and Boon Ang
Thermal management of semiconductor chips is becoming critical as the demand for chip performance increases. It is necessary to evaluate/manage the thermal aspects of a chip throughout the development cycle – starting from initial planning stage to deployment on customer board and beyond. In this paper, we present a versatile thermal evaluation vehicle that addresses the above requirements. This paper describes the architecture, implementation, details of operation, programming aspects, usage model and various applications of a silicon chip that is successfully used as a thermal evaluation tool. The chip has 1600 sectors with programmable heat-generation and temperature-sensing capability – enabling it to generate up to 3W per mm2 and has a temperature detection range of 30C to 125C with an accuracy of +/-2C. It has a simple implementation and is easy to program and test - yet has substantial thermal evaluation capabilities. It was fabricated in 0.18um technology and packaged as flip-chip. The chip has ability to do automated on-chip measurements through a tester-friendly interface and has been successfully controlled through a simple and inexpensive test-platform. The ability to generate heat on-die and monitor spatial & temporal on-die temperature makes this chip suitable to mimic many different use cases of a product during the development stage ahead of product silicon availability. The capabilities of this test-vehicle make it a suitable candidate for demonstrating power-aware/thermal-aware testing. Silicon measurement data and comparison to simulation results based on numerical models are also presented in this paper.
11:50 [6-4] All-Digital Within-Die Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors
Shu Hokimoto, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera
Dynamically scaling the supply voltage (VDD) and the threshold voltage (VTH) is one of the most effective approaches for reducing the energy consumption of processors. With all-digital within-die heterogeneous sensors, we propose a simple runtime method to accurately identify the best pair of VDD and VTH, which minimizes the energy consumption of a processor under a specific operating condition which is determined by a process variation, an activity factor, and a performance requirement for the processor. Measured results for a 32-bit RISC processor integrating the heterogeneous sensors show that the proposed method successfully tracks the minimum energy operating point (i.e. the best pair of VDD and VTH) of the processor even in a case that the operating condition widely varies.
12:10 Lunch
13:30 Invited Talk
14:00 Session 7 Test Parallelism
14:00 [7-1] Addressable test structure design enabling parallel testing of reliability devices
Lee DeBruler, Dennis Pretti, Mike Violette, Dave Peterson, Salil Mujumdar, Xia Li, and Ken Marr
With this paper, we are showing a pad efficient design for testing reliability structures using a multiplex controlled pass gate methodology. This design enables the ability for parallel stressing of all devices and ability to identify precise failing locations. With further engineering of the pass gate this methodology should apply to all semiconductor technologies.
14:20 [7-2] Algorithm Based Adaptive Parametric Testing for Outlier Detection and Test Time Reduction
Veenadhar Katragadda, Martin Muthee, Arthur Gasasira, Frank Seelmann, and Jiun-Hsin Liao
Parallel test capability, enabled by numerous independent measurement channels has significantly increased throughput in parametric testing. It involves testing of numerous devices simultaneously synchronously or asynchronously. The number of devices tested for a given pad layout is increased by using higher dimensional arrays, the hallmark of which is pad sharing. Parallel testing of multiple devices with shared pads is vulnerable to device fails, where a failing device adversely affects measurement of all other devices. Information about this failing device or compromised measurement would only be evident at post analysis where a retest with a recipe change can then be ordered. In some cases retest is impossible as wafers would have already moved on to subsequent processing steps, thereby losing valuable learning opportunity. On the other hand, having to wait for post analysis requires time. Ideally failure detection and subsequent re-measure is done dynamically while the device is under test. This would require that decision making capability to be implemented in an automated tester environment. In this work, we will discuss an algorithm based approach to adaptively change the test program allowing testing or skipping devices based on data collected real time while device is under test.
14:40 ICMTS 2019, Break
15:20 Session 8 Device Characterization
15:20 [8-1] Evaluation of Qss on SOI Back Si/SiO2 Interface by Newly Designed Charge Pumping Method-TEG
Kazuma Takeda, Jiro Ida, Takayuki Mori and Yasuo Arai
The Qss of SOI back Si/SiO2 interfcae was evaluated by newly desiged CP-TEG. The CP method was also re-examied to apply to the thick oxide MOS. It was founded out that the Qss of SOI back interface (bonded wafer interface) is comparabe to that of the thermal oxidation interface.
15:40 [8-2] Quatitative Model of CMOS Inverter Chain Ring Oscillator’s Effective Capacitance and Its Improvements in 14nm FinFET Technology
Seong Yeol Mun, J. Cho, B. Zhu, P. Agnihotri, C.Y. Wong, T.J. Lee, V. Mahajan, B.W. Liu, Y.J. Shi, W. Hong, J. Ciavatti, J.G. Lee, S. B. Samavedam, and D.K. Sohn
The quantitative model of effective total capacitance, Ceff, of a CMOS ring oscillator (R/O) inverter chain in a 14nm node FinFET 3D structure using advanced Replacement Metal Gate (RMG) is successfully extracted using all the unit capacitance components comprising the R/O, such as inverter, fan-out (F/O) MOSCAP, and metal routing. The extracted Ceff model is well validated by perfect matching to the measured Si Ceff in the R/O. This paper provides a concise and clear Ceff quantitative model of inverter R/O chain using individual transistor capacitance components such as channel capacitance (Cgc), overlap capacitance (Cov), junction capacitance (Cj) and metal wire capacitance (Cwire) considering the R/O layout and its operation mechanism, which has never been reported before. Furthermore, Cov is decomposed with the gate to contact capacitance (Cmol), EPI source-drain (S/D) to gate on Fin top (Cft), EPI S/D to gate on Fin sidewall (Cfb) and intrinsic gate to S/D overlap capacitance (Cdo) with Si data and simulation. Contribution to Ceff by all the capacitor components from Cgc, Cmol, Cj, Cwire, Cft, Cfb and Cdo is extracted with Si validation. Cov reduction without DC performance degradation is also provided in this paper.
16:00 [8-3] Measurement of IGBT trench MOS-gated region characteristics using short turn-around-time MOSFET test structures
Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Shinichi Suzuki, Toshihiko Takakura, and Toshiro Hiramoto
Trench MOSFET test structures were fabricated for evaluating IGBT MOS-gated region performance. It was found that the test structures can be used for measuring saturation and sub-threshold current, though accurate estimation of linear resistance is difficult. Charge pumping measurement can be used to evaluate the oxide/substrate interface quality, for possible application to process optimization.
16:20 [8-4] Sensitivity of High-k Encapsulated MoS2 Transistors to I-V Measurement Execution Time
Pavel Bolshakov, Ava Khosravi, Peng Zhao, Paul K. Hurley, Rovert M. Wallace, and Chadwin D. Young
MoS2 FETs encapsulated in a high-k environment were fabricated and electrically characterized. Changes in gate voltage step and measurement speed were introduced and compared to study the effects on the I-V response. This study demonstrated significant changes in subthreshold slope and threshold voltage in part due to charge trapping at the high-k/MoS2 interface, which can alter device performance.
16:40 [8-5] Total Ionizing Dose Effects on Analog Performance of 65 nm Bulk CMOS with Enclosed-Gate and Standard Layout
Matthias Bucher, Aristeidis Nikolaou, Alexia Papadopoulou, Nikolaos Makris, Loukas Chevas, Giulio Borghello, Henri D. Koch, Federico Faccio
High irradiation doses cause significant shifts in design parameters of standard bulk silicon CMOS. Analog performance of a commercial 65 nm CMOS technology is examined for standard and enclosed gate layouts, with Total Ionizing Dose (TID) up to 500 Mrad. The paper provides insight in geometrical and bias dependence of key design parameters such as threshold voltage, DIBL, transconductance efficiency, slope factor, and intrinsic gain.
17:00 End

Day 3 - March 22

09:00 Session 9 MEMS
09:00 [9-1] An On-chip Test Structure for Studying the Frictional Behavior of Deep-RIE MEMS Sidewall Surfaces
R Ranga Reddy, Yuki Okamoto, and Yoshio Mita
An on-chip micro-mechanical test structure has been developed to investigate the friction behavior of Deep-RIE sidewall contacting surfaces of single crystal silicon which is most widely used in micromechanical systems (MEMS). Two orthogonally placed electrostatic comb-drive actuators were adopted to apply the normal load and generate the tangential motion on sidewall surfaces. Through experiments, it was found that with the increment of normal forces, the static friction coefficient is no longer a constant value and it has less effect on dynamic friction coefficient. DRIE process parameters greatly influence the frictional properties on both static and dynamic friction coefficients.
09:20 [9-2] Wafer Level Characterisation of Microelectrodes for Electrochemical Sensing Applications
E.O. Blair, L. Parga Basanta, I. Schmueser, J.R.K. Marland , A. Buchoux, A. Tsiamis, C. Dunare, M. Normand, A.A. Stokes, A.J. Walton and S. Smith
This work presents a system for making measurements of electrochemical sensor test structures at wafer-level. Normally such sensors need to be diced and packaged, but by integrating the characterisation step into the fabrication process, developing electrochemical sensors becomes faster and less expensive. This abstract presents initial measurements demonstrating the capability of making electrochemical measurements on test structures on a probe station.
09:40 [9-3] Test Structure for Electrical Assessment of UV Laser Direct Fine Patterned Material
Naoto Usami, Akio Higo, Ayako Mizushima, Yuki Okamoto, and Yoshio Mita
We propose a test structure to electrically assess direct laser fine patterning, which is entering a microelectronic era (below 10mm). Indium-Tin-Oxide (ITO) was used as a material example. High speed ITO patterning with laser ablation can contribute short turn-around-time development of opto-electrical devices, such as organic light emitting diode. However, not only machine-induced line-edge fluctuation but also the process (e.g. heat) induced material degradation may affect electrical linewidth. The aim of our test structure is to assess such critical dimension change through measurement of electrical property (i.e. conductivity). It consists of Kelvin connection straight lines and Greek crosses with various widths. Ultraviolet (UV) laser process as well as lithography and plasma etching were applied with the same test structure. The measurement revealed that the applied direct patterning condition induced small damage, showing applicability of direct patterning in microelectronics R&D.
10:00 [9-4] Open Model for External Mechanical Stress of Semiconductors and MEMS
R. T. Buehler and R. C. Giacomini
This paper defines the details of the bending equipment solution and the calibration required for characterization of external mechanical stress in semiconductors or MEMS. The equipment is suited for use in probe station for electrical characterization of devices under controlled external mechanical stress.
10:20 Break
10:50 Session 10 Noise & RF
10:50 [10-1] Importance of complete characterization setup on on-wafer TRL calibration in sub-THz range
Chandan Yadav, Marina Deng, Magali De Matos, Sebastien Fregonese, and Thomas Zimmer
In this paper we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test structures combined with on-wafer TRL calibration along with simulation results of intrinsic test structures carried out in HFSS. The limitation of on-wafer TRL calibration is pointed out for some sub-mm and mm-wave probes.
11:10 [10-2] Measurement Time Reduction Technique for Input Referred Noise of Dynamic Comparator
Yuki Ishijima, Shuya Nakagawa, and Hiroki Ishikuro
A measurement technique to reduce the measurement time of input referred noise in dynamic comparator is presented. By using binary search method to detect the standard deviation of input referred noise and offset, proposed technique can reduce the measurement time by a factor of n/log2(n).
11:30 [10-3] System Aware DUT Design for Optimum On-Wafer Noise Measurement
Chih-Hung Chen, Benson Yang, Pei-Hsien Chua, Graham Brown, and Saswati Das
This paper presents a system-aware design of device-under-tests (DUT) for optimum on-wafer noise measurement. It overcomes the challenge due to the voltage drop in the interconnections of a large DUT. It also prevents the inaccuracy from a small DUT. Experimental data and suggested device sizes for different technologies are presented.
11:50 [10-4] Measurement of Temperature Effect on Random Telegraph Noise Induced Delay Fluctuation
A.K.M. Mahfuzul Islam, Masashi Oka, and Hidetoshi Onodera
We present detailed measurement results of temperature effect on Random Telegraph Noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Skewed ring oscillators (ROs) are used to evaluate pMOFSET and nMOSFET specific RTN effects. Furthermore, threshold voltage distributions have been extracted such that the simulated delay distribution matches with the measured delay distributions. Measurement results reveal that with the increase of temperature RTN effect decreases. However, low correlation coefficients of 0:3 to 0:4 have been found between 0C and 80C for different ROs. Low correlation poses challenges in realizing robust runtime performance compensation techniques such as replica critical path based delay compensation.
12:10 Best Paper & Close
14:00 Excursion