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Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Day 1 - March 19

08:00 Registration
09:00 Welcome
09:10 Invited Talk 1
09:40 Session 1 Photonic Test Structures
Co-Chairs: KOVALGIN, Alexey, U. Twente, Netherland
09:40 [1-1] A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies
Akio Higo, Tomoki Sawamura, Makoto Fujiwara, Etsuko Ota, Ayako Mizushima, Eric Lebrasseur, Taro Arakawa, and Yoshio Mita
High-throughput electron beam (EB) lithography technologies such as variable shape beam (VSB) and character projection (CP) are drawing much interests to the industries due to the wafer scale exposure capability and reduced exposure time in the order of magnitude. However, the tradeoff relationship of the exposure quality according to the EB exposure pattern approximation methods has not yet been comprehensively studied. The study is essential for photonics because target patterns include curved shapes. We propose a test structure of silicon racetrack resonator to quantify the quality dependence. Three approximation techniques were tried such as octagon shape CP, tilted square CPs, and thin variable shape rectangles. Optical measurement clearly revealed quality differences between methods, which were impossible to be identified by classical metrological methods including Surface Probe Microscopy (SPM).
10:00 [1-2] PbS Quantum Dot/ZnO Nanowires Hybrid Test Structures for Infrared Photodetector
Haibin Wang, Takaya Kubo, Hiroshi Segawa
A systematic investigation into the performance of PbS quantum dot photodetector using PbS quantum dot/ZnO nanowires hybrid test structure was carried out, and found out that, ZnO nanowires act as a very efficient transporter and collector for the photogenerated electrons in PbS QD region.
10:20 [1-3] In search of a hole inversion layer in Pd/MoOx/Si diodes through I-V characterization using dedicated ring-shaped test structures
G.Gupta, D.T. Shivakumar, R.J.E. Hueting and L.K. Nanver
High workfunction MoOx-based contacts to p- and n-type silicon substrates are investigated employing dedicated ring-shaped test structures. Through systematic electrical measurements, the possible role of a hole inversion layer at the MoOx/n-Si interface is explored. The contact resistivity of the Pd/MoOx-to-Si interface and the MoOx bulk resistivity were also estimated.
10:40 [1-4] Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module
Ye Wang, Hanyi Ding, Barry Blakely, and Aidong Yan
In this paper, we demonstrate a wafer-level sorting test solution developed for quad-channel linear driver, for a 400G silicon photonics transceiver module. In-house built tester-on-a-board (TOB) system was used to provide power and control signals to the DUT, as well as conduct parametric tests. RF switch matrix was implemented to support multi-channel RF tests up to 50GHz. This wafer sorting test solution covers contact tests, power consumption tests, single-ended and true-mode differential full S-parameter tests, and total harmonic tests. This work enables wafer-level driver die sorting capability for next-generation 400G silicon photonics coherent transceiver module.
11:00 Break
11:20 Session 2 Yield & Reliability
Co-Chairs: WEILAND, Larg, PDF, USA
MORI, Shigetaka, SONY corporation
11:20 [2-1] Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive Ring Oscillators
Ryo Kishida, Takuya Asuke, Jun Furuta, and Kazutoshi Kobayashi
Measuring bias temperature instability (BTI) by ring oscillators (ROs) is frequently adopted. However, the performance of a semiconductor chip is fluctuated temporarily due to bias, temperature and etc. BTI-sensitive and -insensitive ROs are implemented in order to extract BTI-induced degradation without temporal fluctuation factors. A test chip including those ROs was fabricated in a 65 nm process. BTI-induced degradation without temporal fluctuation was successfully measured by subtracting results of BTI-insensitive ROs from those of BTIsensitive ones. BTI in NMOS and PMOS transistors increases along logarithmic and exponential functions, respectively.
11:40 [2-2] Extremely Low Voltage Operatable On-Chip-Monitor-Test Circuit for Plasma Induced Damage using High Sensitivity Ring-VCO(Voltage Controlled Oscillator)
Manabu Tomita, Shigetaka Mori, Shinichi Miyake, Kazuhisa Ogawa, Yuzo Fukuzaki, and Hidetoshi Ohnuma
We developed a on-chip-monitor-test circuit that measures Vth fluctuation due to plasma induced damage(PID) during wafer process using ordinary AC test at low Vdd operation condition. The circuit was fabricated on 28nm process and actual measurement experiments were carried out to confirm the measurement principle. We confirmed that it can be operated at low 0.5v Vdd condition comparing 0.9v with previous circuit at same frequency. It can be adopted to IoT low power products beyond 28nm CMOS.
12:00 [2-3] Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions
Mathieu Jaoul, David Ney, Didier Céli, Cristell Maneux and Thomas Zimmer
This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors (LE>>WE) with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.
12:20 Lunch
13:35 Invited Talk 2
14:05 Session 3 Novel Process Characterization
Co-Chairs: YOUNG, Chadwin, University of Texas at Dallas
14:05 [3-1] Electrical characterization of ultra-thin Tungsten films made by novel hotwire-assisted atomic layer deposition
Kees van der Zouw, Antonius A. I. Aarnink, Jurriaan Schmitz and Alexey Y. Kovalgin
In this work, we applied conventional Van der Pauw and circular transmission line method (CTLM) test structures to determine the sheet and contact resistance of ultra-thin (1-10 nm) tungsten films grown by Hot Wire assisted Atomic Layer Deposition, as well as their temperature coefficient of resistance (TCR). We finally explored the field effect (FE) in these layers.
14:25 [3-2] Uniformity assessment for supercritical-fluids-depositted (SCFD) Cu film as electroplating seed layer
Naoto Usami, Etsuko Ohta, Akio Higo, Takeshi Momose and Yoshio Mita
We evaluated supercritical fluid deposition (SCFD) copper thin films as seed layers of electroplating processes. SCFD process is attractive technology for conformal metal coating on high-aspect trench or hole walls. Therefore, it has great potential for an electroplating seed layer. To utilize SCFD films as seed layers, we assessed the electrical and topological uniformity of the SCFD films. The electrical measurements efficiently identified suitability of various SCFD films to the electroplating process, which has been difficult by microscope observation. The results have been cross-validated by atomic force microscopy.
14:45 [3-3] Test structures for characterising the silver chlorination process during integrated Ag/AgCl reference electrode fabrication
C. Dunare, J.R.K. Marland, E.O. Blair, A. Tsiamis, J.G. Terry, A.J. Walton, S. Smith
Robust and repeatable processes are required to fabricate reference electrodes for microscale integrated electrochemical sensors. One method for this is to produce a “silver/silver chloride” (Ag/AgCl) electrode through chemical chlorination of a thin film silver layer. This paper presents initial work using electrical resistance measurements to monitor the chlorination process as well as a new test chip design for future process development and control.
15:05 [3-4] Test structures to assess the useful extent of regular dummy devices around high-precision backend metal fringe capacitor arrays
Hans Tuinhout, Ihor Brunets and Adrie Zegers-van Duijnhoven
This paper discusses test structures that assess the impact of subtle layer density disturbances at the edges of arrays of high-precision matched backend metal fringe capacitors. It is demonstrated that a seemingly minor pattern density disturbance can significantly affect the matching performance of capacitors up to over 5 ?m away from the array edges.
15:25 Exhibitor Presentation
15:55 Break
16:10 Session 4 Resistive Materials
Co-Chairs: SMITH, Stewart, U. Edinburgh, UK
HESS, Christopher, PDF, USA
16:10 [4-1] Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials
T. Maeda, Y. Omura, A. Teramoto, R. Kuroda, T. Suwa, and S. Sugawa
A newly developed resistance measurement platform is presented in this paper. The measurement platform consists of an array test circuit fabricated by a conventional 0.18 ?m 1-Poly-Si 5-Metal layers CMOS technology, and a measurement target material formed on top of the 5M layer of the platform by an additional process. Using this platform we can measure the resistance of various materials only by forming the measurement target layer and the top metal layer on the platform additionally. The resistance measurement operation was verified by measuring 234 poly-Si test resistor pre-formed by the poly-Si gate electrode layer in the array test circuit. Furthermore, 200 nm thick amorphous-Si layer was formed as a measurement target material on the platform and 490,700 cells were measured. We observed random telegraph noise (RTN) in some amorphous-Si cells. The resistance measurement of 490,700 cells was conducted within 0.5 s with the resistance range of 500 ? - 10 M?. The developed platform is very useful for research and development of new memory materials, as well as for developing process, process equipment, and device structure to improve the reliability and performance of next generation memories.
16:30 [4-2] Optimization of 30mega method for Phase-Change Materials Thermal Conductivity Measurement at High Temperature
Anna Lisa Serra, Guillaume Bourgeois, Marie Claire Cyrille, Jacques Cluzel, Julien Garrione, Gabriele Navarro and Etienne Nowak
Abstract: Thermal conductivity (kth) of Ge-rich Ge2Sb2Te5 phase-change material (GGST) is investigated at temperatures up to 400 °C through “3? method”. We present the engineering of the test vehicle, with the optimization of the heater to achieve a reliable measurement even at high temperature. Finally, we compare the results from four different approaches for the kth evaluation.
16:50 [4-3] Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips
Christopher Hess, Tomasz Brozek, Hendrik Schneider, Yuan Yu, Meindert Lunenborg Khim Hong Ng, Dennis Ciplickas, Rakesh Vallishayee, Larg H. Weiland
More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow Characterization Vehicle (CV) Test Chips can be used to enable fast yield and endurance learning cycles. However, billions of bit cells have to be measured which requires access to more than just one bit cell per pad to be economically viable. Since, there are no FEOL switches available to address the bit cells we are evaluating truly Passive Crossbar Memory Arrays (PCMA) to significantly improve the bit per area ratio. Experimental results confirm successful memory operation based on fast parallel pulse testing. Design and chip floor planning guidelines are presented to balance bit cell sample size, array size, signal to noise ratio, and test time.
17:10 [4-4] Proposed One-Dimensional Passive Array Test Circuit Architecture for Parallel Kelvin Measurement with Efficient Area Use
M. Rerecich and C. Young
Massively parallel parametric testing opens reassessment of design tradeoffs for on-wafer parametric test between the three competing requirements of test accuracy, volume, and speed. This paper proposes a one-dimensional passive array to accomplish kelvin resistance measurement of all connected devices, in parallel, and with only two independent pads per device.
17:30 End of 1st day

Day 2 - March 20

08:00 Registration
08:30 Bonus Talk 1
Colin McAndrew
09:00 Invited Talk 3
09:30 Session 5 Power Device
Co-Chairs: OHGURO, Tatsuya, Toshiba, Japan
09:30 [5-1] Vertical Bipolar Transistor Test Structure for Measuring Minority Carrier Lifetime in IGBTs
K. Takeuchi, M. Fukui, T. Saraya, K. Itou, T. Takakura, S. Suzuki, Y. Numasawa, K. Kakushima, T. Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, H. Wakabayashi, M. Tsukuda, A. Ogura, K. Tsutsui, H. Iwai, S. Nishizawa, I. Omura, H. Ohashi, and T. Hiramoto
Vertical PNP bipolar transistor test structures were fabricated, which can be integrated on the same wafer with functional IGBTs. Common-base current gain was measured by applying zero voltage to the leaky back side junction, from which minority carrier lifetime in the base region was extracted. The structure makes it possible to measure the lifetime after real IGBT fabrication process, and to compare it with the characteristics of IGBTs on the same wafer.
09:50 [5-2] Modeling and Test Structures for Accurate Current Sensing in Vertical Power FETs
Min Chu, Tikno Harjono, Kuntal Joardar, and Vijay Krishnamurthy
A new approach using a combination of analytical models, Spice simulations, and test structures is reported that allows for a comprehensive treatment of 3D distributed effects in vertical power FETs, leading to higher accuracy in current sensing as well as more cost- and time-efficient design cycles.
10:10 [5-3] A study on statistical parameter modeling of power MOSFET model by principal component analysis
Hiroki Tsukamoto, Michihiro Shintani, and Takashi Sato
A dominant model parameter set that largely contributes characteristic variation of a power MOSFET has been studied through principal component analysis. Through the experiment using measured drain currents of 40 SiC power MOSFETs, the fluctuation of the current characteristics can be represented by three parameters.
10:30 Break
10:50 Session 6 Matching & Variability
Co-Chairs: TUINHOUT, Hans P., NXP, Netherlands
FUKUZAKI, Yuzo, Sony Corporation
10:50 [6-1] Two-transistor Test Structure for the Extraction of sigma (delta beta / beta) and sigma (delta VTH) MOS Mismatch Parameters based on Voltage Measurements
Juan Pablo Martinez Brito, Sergio Bampi
This work proposes to measure transistor mismatches with the combination of two stacked MOS transistors and a measurement methodology that relies on two single spot voltage measurements. The method allows to separately extract ?(?VTH) and ?(??/?) with an error less than 2% and an increase of 30x in measurement speed.
11:10 [6-2] On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch
Poorvi Jain and Bishnu Prasasd Das
In this work, an all-digital on-chip threshold voltage variability detector that uses single ring oscillator (RO) with compact size is proposed to detect the local random threshold voltage variation from an array of device under test (DUTs). A direct correlation between the threshold voltage variation of DUT and the voltage at sense node which is the supply of RO, is achieved. The difference in RO period due to change in voltage level from VDD to (VDD-VTH) at the sense node actually represents the threshold voltage of a DUT. The detection of threshold voltage of a DUT from RO period difference is possible by creating an exponential relationship between the two. The difference nature of estimation technique enables to mitigate the impact of local supply variation and systematic background noise as RO have common path. The potency of the proposed technique is demonstrated using measurement results from a test chip designed in a 0.13?m process technology node. Measurement results from 26 fabricated test chips indicate that the test structure can estimate local random threshold voltage variations with weak inter-die and intra-die spatial correlation and is also useful in improving the yield as well as in process optimization.
11:30 [6-3] Evaluation of Threshold Voltage Extraction Methods with Temperature Variation
Yu-Hsing Cheng
Multiple threshold voltage extraction methods are compared and evaluated with experimental data over a wide temperature range from -40°C to 150°C for 1.8V and 5V MOS devices in a 0.18?m BCD process. The different trends of scaled currents at extracted threshold voltage are identified for linear extrapolation versus gm/Id methods.
11:50 [6-4] Analysis of test structure design induced variation in on Si On-wafer TRL calibration in sub-THz
Chandan Yadav, Sebastien Fregonese, Marina Deng, Marco Cabbia, Magali De Matos,Thomas Zimmer
In this paper, we present measurement of very high frequency dedicated test structures designed and fabricated on silicon substrate for calibration and de-embedding. With On-wafer TRL calibration using two different type of reflects (open and short), we show that theoretical predictions may not always be true in the On-wafer calibration. Through On-wafer TRL calibrated S-parameters of de-embedding structures, we conclude that one type of reflect could suit more in On-wafer TRL for a de-embedding structure than another type.
12:10 Lunch
13:20 ICMTS 2020
13:30 Session 7 Measurement Technique
Co-Chairs: VERZI, Bill, Keysight, USA
13:30 [7-1] A Study of Power Supply Stability in Ring Oscillator Structures
Brad Smith, Donald Hall, Bill Verzi, and Dan Pechonis
The stability of the power supply rails while testing wafer-level ring oscillator structures has been studied. The power and ground supplies were observed to be disturbed by a switching output signal, a result of the tester hardware being unable to respond fast enough to maintain stable voltages. It was shown that using stronger test hardware to provide 0 V improved the stability of the ground voltage. It was further shown that the addition of discrete capacitors between the power supplies improved the stability of the supply voltage. The areas under curves in the supply voltage waveforms were used as quality metrics to quantify the charge involved in the disruption and to evaluate different solutions.
13:50 [7-2] Fast Tera-ohm measurement approach using V93k AVI64 DC scale card
Joern Stolle, Regis Poirier, Martin Froehle, Hermann Weindl, and Martin Naiman
This paper describes a measurement approach to measure Mega-ohm resistor and Giga-ohm isolation structures using low power test conditions with V93k AVI64 equipment. It was also possible to detect resistor values up to a few Tera-ohm. Compare to a dedicated parametric benchmark tool, we are approx.. 5x faster within a high accuracy and repeatability.
14:10 [7-3] A Study of Test Throughput Analysis on Capacitance Measurement of Parallel Test Structures using LCR and Direct Charge based Instruments
Veenadhar Katragadda, Namita Deshmukh, Arthur Gasasira, Cheng-Mao Lee, Alan Cusick
Advancement in technology scaling has enabled further integration of more structures per area. While the direct benefits of improved performance in smaller packaging is achieved, the test content per structure has increased for quicker and better yield learning, ultimately driving up test time and cost. Parallel testing where multiple DUT’s can be measured synchronously or asynchronously has shown results in addressing such high test demand [1][2]. In this paper, we will discuss capacitance measurement using traditional LCR meter and direct charge measurement (DCM) hardware [3] on advanced technology nodes. The LCR meter is a shared resource whereas DCM is per-pin based capacitance measurement unit, enabled for higher throughput [3]. We present analysis using two types of DCM hardware, one limiting to 1uS conductance and other with a wider range up-to 1mS. We discuss a thorough analysis of correlation as shown in figure 1 and throughput shown in figure 2 to traditional LCR measurements. We introduce an adaptive algorithm [4], capturing several ranges of conductance/leakage compensation, providing better understanding of wafer throughput. We show that the structures Designed for Parallel Test (DFPT), deliver higher throughput when tested using WRPCMU.
14:30 [7-4] Characterization and Modeling of Zener Diode Breakdown Voltage Mismatch
Man Yang, Colin C. McAndrew, Lei Chao, and Kejun Xia
In this paper, we present test structures and procedures to characterize and model mismatch of the breakdown voltage of Zener diodes. Direct force-current/measure-voltage for breakdown is not sufficiently accurate for mismatch characterization, so we use an ????(????) sweep followed by cubic interpolation; the accuracy of this approach is verified using the Tuinhout DUT-1-2-1-2 methodology. To demonstrate our approach, we present measured and modeled breakdown voltage mismatch for 5V Zener diodes in a 90 nm power BCD process.
14:50 [7-5] Physical, small-signal and pulsed thermal impedance characterization of multi-fingers SiGe HBTs close to the SOA edges
Marine Couret, Gerhard Fischer, Sébastien Frégonèse, Thomas Zimmer and Cristell Maneux
A thermal impedance model of single-finger and multi-fingers SiGe heterojunction bipolar transistors (HBTs) is presented. The heat flow analysis through the device has to be considered in two diffusion parts: the front-end-of-line (FEOL) diffusion and the back-end-of-line (BEOL) diffusion. Therefore, this new thermal impedance model features multi-poles network which has been incorporated in HiCuM L2 compact model. The HiCuM compact model simulation results are compared with on-wafer low-frequency S-parameters measurements at room temperature highlighting the device frequency self-heating behavior. The simulation results are also compared to pulse measurements to discriminate self-heating effects from others transport mechanisms such as impact ionization.
15:10 Break
15:30 Session 8 Noise
Co-Chairs: TAKEUCHI, Kiyoshi, U. Tokyo, Japan
15:30 [8-1] Experimental Extraction of Body Bias Dependence of Low Frequency Noise in Sub-micron MOSFET from Sub-threshold to Moderate Inversion Regime
Chika Tanaka, Kanna Adachi, Atsushi Nakayama, Yasuhiko Iguchi, and Sadayuki Yoshitomi
15:50 [8-2] Effect of Logic Depth and Switching Speed on Random Telegraph Noise Induced Delay Fluctuation
A.K.M. Mahfuzul Islam, Ryota Shimizu, and Hidetoshi Onodera
We present detailed measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Minimum sized ring oscillators (ROs) are used to characterize RTN effect on delay fluctuation in delay paths. Measurement results reveal that the rate of decrease in delay fluctuation is much higher than the static random variation with the increase of logic depth. Furthermore, RTN effect tends to decrease with the decrease in switching speed. Thus, the measurement results provide useful insights into assessment of worst-case delay under the presence of RTN.
16:10 [8-3] A Method to Determine the Electret Charge Potential of MEMS Vibrational Energy Harvester using Pure White Noise
Hiroyuki Mitsuya, Hisayuki Ashizawa, Hiroaki Homma, Gen Hashiguchi, and Hiroshi Toshiyoshi
A new measurement method is developed to determine the electrical potential of electret embedded in a MEMS vibrational energy harvester. The method is to electrically excite the device with white noise voltage while sweeping the static bias voltage. The mechanical resonance disappears when the electret potential is compensated by the applied bias voltage.
16:30 Break
17:45 Departure for Moji port by boat
19:00 Banquet
22:00 Return from Moji port
22:00 End of 2nd day

Day 3 - March 21

08:00 Registration
08:30 Bonus Talk 2
Yoshio Mita
09:00 Session 9 Packaging
Co-Chairs: HABU, Satoshi, Keysight, Japan
09:00 [9-1] Probing Impact on Pad Moisture Tightness: a Challenge for Pad Size Reduction
Matthias Vidal-Dhô, Quentin Hubert, Patrice Gonon, Philippe Delorme, Jonathan Jacquot, Maxime Marchetti, Ludovic Beauvisage, Jean-Michel Moragues, Pascale Potard, Pascal Fornara, Jean-Philippe Escales, Pascal Sallagoity, Olivier Pizzuto, Delphine Maury, Jean-Michel Mirabel
This paper underlines the damages induced by probing on narrow pads reliability of specifically designed test structures placed on dicing streets and indicates that probing provokes detrimental cracks diving from the passivation through the BEOL layers providing a path for moisture ingress.
09:20 [9-2] Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests
Choon Beng Sia
The strong market demands to embed different functionalities from various semiconductor processing technologies into a single system continue to drive demands for 3DIC, in particular, shrinking micro-bump sizes to facilitate stacking of multiple dies. Probecards and Single DC probes are unable to address the measurement flexibilities and challenges needed for micro-bump wafer acceptance tests. In this paper, custom DC positioners with theta-X planarizing capability and true Kelvin probes have allowed for successful demonstration of consistent and repeatable test results in fully automatic micro-bump wafer acceptance tests.
09:40 [9-3] Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs Summary
Yuki Okamoto, Ayako Mizushima, Naoto Usami, Jun Kinoshita, Akio Higo, Yoshio Mita
We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of 16×16 arrayed PMOSFETs designed with 0.6 ?m CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of ID-Vg were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place test pads over an LSI chip.
10:00 [9-4] Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events
Matt Lauderdale, Emmanuel Onyegam, Scott Ruth, Brad Smith and Alex Gerdemann
New wafer technologies and chip design requirements are increasingly susceptible to damage from smaller Electro Static Discharge events (ESD). A method is needed to evaluate ESD risk posed by processing equipment and the effectiveness of proposed upgrades. This paper proposes and investigates a packaged test structure designed to measure ESD events. The test chip would run in the place of production parts during equipment and package level process evaluations. A design is proposed, developed and preliminary test results demonstrating feasibility are shown.
10:20 Break
10:40 Session 10 TFTs
Co-Chairs: CAGLI, Carlo, CEA/LETI, France
10:40 [10-1] Understanding the Effects of Low-Temperature Passivation and Annealing on ZnO TFTs Test Structures
Rodolfo A. Rodriguez-Davila, Pavel Bolshakov, Chadwin D. Young, and Manuel Quevedo-Lopez
Back-gate ZnO TFTs – with and without top-side passivation – were fabricated and electrically characterized. Passivation layers consisting of HfO2, Al2O3, and Parylene were introduced to study their impact on the TFT performance. Annealing was done to improve the electrical characteristics of passivated devices by neutralizing the initial charge introduced as a result of the low-temperature passivation. Low-temperature annealing combined with an Al2O3 passivation layer demonstrates an I-V response comparable to ZnO TFTs without any passivation layer, indicating the viability of Al2O3 as a good candidate for passivating ZnO TFTs.
11:00 [10-2] A compact model of I-V characteristic degradation for organic thin film transistors
Michiaki Saito, Michihiro Shintani, Kazunori Kuribara, Yasuhiro Ogasahara, and Takashi Sato
We propose a current model for simulating organic thin film transistors. On the basis of the measurement results, the proposed model characterizes transient degradation of the current through threshold voltage and carrier mobility. With the extracted parameters, the proposed model successfully reproduces performance degradation of the fabricated devices.
11:20 Best Paper Award
11:30 Closing Remarks
11:40 End of Conference
12:00 Optional Tour
By tradition of the ICMTS, the committee proposes to participants to stay over and visit the city. Kita-kyushu city is known as one of the original cities of modern industry in Japan of 20st century. The tour is in English.