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Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Day 1 - March 28

09:00 Session 1 Emerging Memory
09:00 [1-1] Discrete current limiting circuit for emerging memory programming
Léo Laborie1, Paola Trotti1, Killian Veyret1, Carlo Cagli2

1 Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France
2 STMicroelectronics, Grenoble, France
This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The cycling of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.
09:20 [1-2] Test Methodology Development for Investigating CeRAM at Elevated Temperatures
A. A. Gruszecki1, R. Prasad1, S. V. Suryavanshi3, G. Yeric3, and C. D. Young1,2

1 Electrical and Computer Engineering Department, The University of Texas at Dallas, Richardson, Texas, USA
2 Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas, USA
3 Cerfe Labs, Austin, Texas, USA
Correlated electron RAM (CeRAM) device test structures utilizing C-doped NiO were fabricated and electrically characterized to determine functionality in extreme environments. CeRAM devices were demonstrated to repeatedly cycle at temperatures up to 200oC while maintaining a substantial memory window of over 1000x. Careful selection of compliance current when sweeping the high resistance state (OFF) is required for optimal device performance. The presence of a temperature dependent leakage current in the OFF state results in reducing OFF resistance at elevated temperatures.
09:40 [1-3] Real-time electrical measurements during laser attack on STT-MRAM
Nicole Yazigy1, Jeremy Postel-Pellerin1, Vincenzo Della Marca1, Ricardo. C. Sousa2, Anne-Lise Ribotta3, Gregory Di Pendina2, Pierre Canet1

1 Aix-Marseille Université, IM2NP, CNRS, UMR 7334, 5 rue Enrico Fermi, 13397 Marseille, France
2 SPINTEC, University Grenoble Alpes, CNRS, CEA, SPINTEC, 38000 Grenoble, France.
3 Mines Saint-Etienne, CEA, Leti, Centre CMP, 13541 Gardanne, France
The goal of the study is to monitor the device's response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.
10:00 [1-4] Automated RRAM measurements using a semi-automated probe station and ArC ONE interface
Alin G. Panca1, Alexantrou Serb1, Spyros Stathopoulos1, Suresh K. Garlapati2, Themis Prodromakis1

1 Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK
2 Materials Science And Metallurgical Engineering, Indian Institute of Technology Hyderabad, Telangana, India
Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-automated RRAM device testing platform.
10:20 [1-5] Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device
Shih-Kai Lin1, Ting-Chang Chang2,3, Wei-Chen Huang2, Yung-Fang Tan4, and Chen-Hsin Lien1

1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan
2 Department of Physics, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan
3 College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan
4 Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan
High resistance state (HRS) resistance on the set voltage in hafnium oxide-based resistance random access memory (RRAM) is investigated. Set voltage has a positive correlation to HRS in statistics. For analyzing the switching characteristics at different HRS resistance level, filament properties in the switching layer are analyzed by current-fitting technique. The fitting results show that Schottky distance becomes saturated at high resistance HRS. Finally,
11:10 Session 2 Noise
11:10 [2-1] Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure
Owen Gauthier1,2, Sébastien Haendler1, Ronan Beucher1, Patrick Scheer1, Quentin Rafhay2, and Christoforos Theodorou2

1 STMicroelectronics, Crolles, France
2 Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, IMEP-LAHC, Grenoble, France
The use of an addressable array test structure designed on a 28 nm FD-SOI technology for the variability analysis of static, low frequency noise (LFN) and Random Telegraph Noise (RTN) matching is presented. The experimental setup was validated, and a statistical analysis of the above electrical quantities is provided. Using such structures, combined with a switching matrix, local and global variability analysis can be performed while significantly increasing the number of samples, thus enabling a better description of the variations in LFN and RTN, especially when RTN signatures can be scarce. We show that local variations dominate the noise variability compared to global variations.
11:30 [2-2] An Extended Method to Analyze Boron Diffusion Defects in 16 nm Node High-Voltage FinFETs
Ting-Tzu Kuo1, Ying-Chung Chen1, Ting-Chang Chang2,Fong-Min Ciou3, Chien-Hung Yeh4, Po-Hsun Chen5, and Simon M. Sze6

1 Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
2 Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan
3 Department of Physics, National Sun Yat-sen University, Kaohsiung, 80424, Taiwan
4 Department of Photonics, National Sun Yat-sen University, Kaohsiung 804, Taiwan
5 Department of Applied Science, R. O. C. Naval Academy, Kaohsiung 813, Taiwan
6 Department of Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, 300, Taiwan
This work proposed extended methods, which can analyze kinds of defects more easily with power spectrum density (PSD) and weighted time lag plot (W-TLP), to decouple single or multi-traps. To get additional high voltage tolerance, it is common to design different kinds of structures dispersing the electric field. In this work, boron and fluorine were doped in the source and drain extension regions to achieve higher voltage operation. However, boron diffusion could worsen the interface quality. Interestingly, after different stress conditions of hot carrier degradation (HCD) and positive bias temperature instability (PBTI), the degradation trends of the two devices show opposite behaviors. It is because the boron can bear the high voltage operation, but also weak the devices’ interface quality. Therefore, to analyze the influence of these defects plays an important role. With Agilent B1530A WGFMU and RTSDataAnalysis software, varied defects response to frequency can be simply detected. It can also use W-TLP to decouple single trap and multi-traps behaviors at the same time.
11:50 [2-3] Vss-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-In
Kunyang Liu, Yichen Tang, Shufan Xu, and Hirofumi Shinohara

Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan
In this paper, a method to observe random telegraph noise in a hybrid SRAM PUF array is presented. This allows low-cost observation of RTN in a number of bitcells by applying VSS bias voltages to measure their temporal mismatches. Also, the changes in RTN amplitude after hot carrier injection burn-in, which is used for PUF stabilization, have been measured and analyzed. Experimental results from a 130-nm CMOS test chip show that the average RTN amplitude across 80-run measurements increases from 1.46 mV before HCI to 9.72 mV after 18-min HCI. The maximum RTN amplitude also increases from 10.13 mV to 84.50 mV. These results indicate that RTN is not an omittable factor especially for a PUF using a hot carrier injection-based stabilization technique and should be carefully considered when deciding the burn-in strategy.
14:10 Session 3 Power Devices
14:10 [3-1] Distributed field plate effects in split-gate trench MOSFETs
R. Tambone1,2, A. Ferrara1, F. Magrini3, A. Hoffmann3, A. Wood1, G. Noebauer1, E. Gondro3, and R.J.E. Hueting2

1 Infineon Technologies Austria AG, Siemenstrasse 2, 9500 Villach, Austria
2 University of Twente, Drienerlolaan 5, 7522 NB Enschede, The Netherlands
3 Infineon Technologies AG, Am Campeon 1, 85579 Neubiberg, Germany
Fast electric transients can cause distributed effects inside trench MOSFETs possibly resulting in device failure. A new test structure to study those distributed effects, combined with a new Transmission-Line Pulse (TLP) setup, is presented. On-wafer TLP measurements are performed and combined with TCAD and SPICE simulations to predict the space and time evolution of the field plate potential during transients.
14:30 [3-2] Measuring of parasitic resistance of stacked chip of Si power device
Tatsuya Ohguro1, Hideharu Kojima1, Takuma Hara1, Tatsuya Nishiwaki2 and Kenya Kobayashi1

1 Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan
2 Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Stacked chip of Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.
14:50 [3-3] New Extraction Method for Intrinsic Qrr of Power MOSFETs
T. Hara, S. Nakajima, T. Ohguro and K. Miyashita

Advanced Semiconductor Device Development Center, Toshiba Electronic Devices & Storage Corporation
We provide the method to estimate intrinsic Qrr(Qrr_int) without parasitic inductance in the measurement system for the first time. In this paper, we analyze parasitic inductance dependence of Qrr by TCAD simulation and we propose the method for removing the parasitic inductance effect as well as calculating the carrier of recombination and discharge (qrr_int0).
15:10 [3-4] On-Resistance Measurements of Low Voltage MOS-FET at wafer level
Kohei Oasa1, Tatsuya Nishiwaki1, Tatsuya Ohguro2, Yasunobu Saito1, and Yusuke Kawaguchi2

1 Toshiba Electronic Devices & Storage Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
2 Toshiba Electronic Devices & Storage Corporation, 1-1, Iwauchi-Machi, Nomi, Ishikawa, Japan
To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.
15:30 [3-5] Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation
Pei-Yu Wu1, Xin-Ying Tsai2, Ting-Chang Chang3, Tsung-Ming Tsai1 and Simon M. Sze2

1 Pei-Yu Wu and Tsung-Ming Tsai are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan
2 Xin-Ying Tsai and Simon M. Sze are with the Department of Electronics Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan
3 Ting-Chang Chang is with Department of Physics, and also with College of Semiconductor and Advanced Technology Research, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan
In GaN-based metal-insulator-semiconductor high electron mobility transistors (GaN based MIS HEMTs), Al2O3/Si3N4 bilayer-gate insulator-MIS HEMTs (Al2O3/Si3N4-MIS HEMTs) are considered to have the advantages of low gate leakage and low interface defects. This study will compare Si3N4 gate insulator-MIS HEMTs (Si3N4-MIS HEMTs) to discuss and clarify the abnormal deterioration mechanism of Al2O3/Si3N4-MIS HEMTs under Hot Carrier Effect (HCE). Therefore, in this study, the results of HCE between Si3N4-MIS HEMTs and Al2O3/Si3N4-MIS HEMTs are compared, and the abnormal HCS degradations in Al2O3/Si3N4-MIS HEMTs are discussed and explained in depth. A series of electrical and simulation analysis is conducted in order to verify the degradation mechanism model proposed in this study.
16:20 Session 4 Measurement Technique
16:20 [4-1] The Pressing Probe Needle Technique for Characterizing Mechanical Stress Sensitivity of Semiconductor Devices
Hans Tuinhout, Oliver Dieball

NXP Semiconductors, Eindhoven, The Netherlands
This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and high-spatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.
16:40 [4-2] A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure for evaluation of interface uniformity of the Ti-Al alloy/p-type 4H-SiC contact
Yen-Ling Chen, Shih-Hao Lai, Jian-Hao Lin, and Bing-Yue Tsui

Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C.
A multi-contact six-terminal cross-bridge Kelvin resistor (CBKR) structure is proposed to characterize the Ti-Al alloy/p-type 4H-SiC contact. It is confirmed that the test structure can judge the uniformity of the contact interface without destructive analysis such as cross-sectional transmission electron microscopy. Comparing with the results of singlecontact CBKR structure, it is observed that the contact interface is non-uniform and the formation of low resistivity interface depends on the contact area. This area-dependence issue should be solved in order to improve the SiC power devices and CMOS ICs.
17:00 [4-3] Test Structure for Evaluation of Pad Size for Wafer Probing
Brad Smith1, Donald Hall1, and Garrett Tranquillo2

1 NXP Semiconductors, Austin, TX, USA
2 Celadon Systems, Inc., Burnsville, MN, USA

A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100% probe yield.
17:20 [4-4] Test Bench for Biopotential Instrumentation Amplifier using Single-Ended to Differential Amplifiers
Surachoke Thanapitak, Pongsatorn Sedtheetorn, Pornchai Chanyagorn, Tatcha Chulajata, Somnida Bhatranand, and Phattanard Phattanasri

Department of Electrical Engineering, Faculty of Engineering, Mahidol University Nakhon Pathom, Thailand
A practical test bench for dry electrode bio-signal instrumentation amplifier is presented and demonstrated. By modifying the on-the-shelf single-ended to differential amplifier, the common-mode rejection ratio and distortion under electrodes offset scenario can be characterized. The other essential parameters such as input impedance and power supply rejection ratio can also be determined.

Day 2 - March 29

How to make better abstract
09:00 Session 5 Matching & Variability
09:00 [5-1] Measurement of Temperature Effect on Comparator Offset Voltage Variation
Yuma Iwata, Takehiro Kitamura, and Mahfuzul Islam

Department of Electrical Engineering, Graduate School of Engineering, Kyoto University, JAPAN
Comparator offset voltage often limits the performance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100 degree C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100 degree C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.
09:20 [5-2] Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible?
Kiyoshi Takeuchi1, Tomoko Mizutani1, Takuya Saraya1, Masaharu Kobayashi1,2, and Toshiro Hiramoto1

1 Institute of Industrial Science, The University of Tokyo, Tokyo, Japan
2 System Design Research Center (d.lab), The University of Tokyo, Tokyo, Japan
Source-to-drain series resistance (R SD) of a large number of identically designed MOSFETs was extracted using a recently proposed single-device method. By examining statistical correlations with other device parameters, it was confirmed that variability of the extracted R SD values does not correspond to real series resistance variability, but is mainly caused by some non-R SD variability sources. This suggests that, for the single-device method to work, non-R SD variability needs to be reduced by averaging multiple devices, or using wide channel devices.
09:40 [5-3] Variability Evaluation of MOS-gated PNPN Diode for Hardware Spiking Neural Network
Toshihiro Takada, Takayuki Mori, and Jiro Ida

Division of Electrical Engineering, Kanazawa Institute of Technology, Ishikawa, Japan
The variability of the neuronal function device of a metal oxide semiconductor-gated PNPN diode was evaluated. The variability of neurons is known to affect the inference accuracy of spiking neural networks (SNNs). The device has stochastic operation on its own, and the spike requency can be controlled by the gate voltage, which has the possibility to improve the accuracy of SNNs.
10:00 [5-4] Effect of Quadruple Size Transistor on SRAM Physically Unclonable Function Stabilized by Hot Carrier Injection
Shufan Xu1, Kunyang Liu2, Yichen Tang1, Ruilin Zhang1, and Hirofumi Shinohara2

1 Information, Production and Systems Research Center, Waseda University, Kitakyushu, Japan
2 Graduate School of Information, Production and Systems, Kitakyushu, Japan
This article presents a bitcell of a static randomaccess memory (SRAM)-based physically unclonable function (PUF) with quadruple-size transistor, which reduces the ‘tail’ of mismatch distribution after hot carrier injection (HCI) burn-in. A statistical mismatch distribution model after HCI application for a certain time is proposed by combining native mismatch distribution before HCI and mismatch shift distribution after HCI. Model calculation shows that quadruple-size transistor SRAM PUF needs 15-min HCI burn-in time to achieve cryptographic level requirement, which is more than 3 times shorter than normal-size transistor SRAM PUF of 46-min. The effect of utilizing the quadruple-size transistor with respect to HCI burn-in for stability reinforcement is also confirmed by measuring chips fabricated in a 130-nm CMOS process. Experimental results show that the ‘tail’ in mismatch distribution is significantly eliminated after 18-min HCI burnin time of quadruple-size transistor SRAM PUF, which meets our expectations. The presented statistical model also matches the measurement data well.
10:50 Session 6 Yield and Device Optimization
10:50 [6-1] Test Circuit Design for Accurately Characterizing Cells’ Output Currents in a Read-Decoupled 8T SRAM Array for Computing-in-Memory Applications
Hao-Chiao Hong1,2, Long-Yi Lin1,3, and Bo-Chang Chen2

1 Institute of Electrical and Computer Engineering,
2 Institute of Electrical and Control Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan
3 Novatek MicroElectronics Corp., Hsinchu, Taiwan
Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.
11:10 [6-2] Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation
V.Vidya1, N. Zamdmer1, T. Mechler1, K. Onishi1, D. Chidambarao1, B. W. Jeong2, Y. G. Ko2, C. H. Lee1, J. Sim1, M. Angyal1, E. Crabbe1

1 IBM Systems, IBM Corp, 2070 Route 52, B300-A, Hopewell Junction, NY 12533, USA
2 Samsung Electronics Co. Ltd, San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea
This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.
11:30 [6-3] An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology
Hai Zhu1, Katsunori Onishi1, Stephen Wu1, Adam Yang1, Byoung-Wook Jeong2, Seong-Joon Lim2, Nan Jing1, Choong-Ho Lee1, David Conrady1, and Dureseti Chidambarrao1

1 IBM Systems, IBM Corp, 2070 Route 52, B300A, Hopewell Junction, NY 12533, USA
2 Samsung Electronics Co. Ltd., San#16, Banweol-Dong, Hwasung-City, Gyeonggi-Do, 445-701, Republic of Korea

On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.
11:50 [6-4] Wafer Level Reliability Monitoring of NBTI Using Polysilicon Heater Structures for Production Measurements
Yu-Hsing Cheng

Central Engineering, onsemi 1900 South County Trail, East Greenwich, RI 02818, USA
The use of polysilicon heater structures provides a useful tool for fast NBTI assessment of wafer level reliability. In this work NBTI characterization for 1.2V PMOS devices in a 65 nm technology using polysilicon heaters in a parametric tester was performed without changing the chuck temperature to demonstrate NBTI reliability assessment with a short test time for production measurements.
How to make better presentation ; 30 min
ICMTS 2024 ; 15 min
Coffee Break ; 30 min
14:55 Session 7 MEMS & Sensors
14:55 [7-1] Application of Greek cross structures for process development of electrochemical sensors
Minxing Zhang1, Shan Zhang1,2, Camelia Dunare1,2, Jamie R. K. Marland1,2, Jonathan G. Terry1,2, Stewart Smith1,3

1 School of Engineering, The University of Edinburgh, Edinburgh, Scotland, UK
2 Research Institute for Micro and Nano Systems
3Research Institute for Bio-Engineering
Using a test structure chip designed to assist in process development for reference electrode fabrication for integrated electrochemical sensors, this paper reports measurements of Greek cross test structures and compares them to measurements of bridge resistor structures on the same chip. The correct application of these structures requires careful consideration of the measurement parameters to provide accurate results and different force current values have been investigated. Results from platinum structures suggest there is measureable variation in the feature size when Greek cross results are used to extract electrical critical dimension from the bridge resistor measurements. Similar measurements of silver structures were less conclusive. While the bridge structures show a significant effect of oxidation of silver which has been exposed to air since fabrication, the Greek cross results are highly variable and may not be reliable.
15:15 [7-2] Test Structures for Studying Coplanar Reverse- Electrowetting for Vibration Sensing and Energy Harvesting
Anotidaishe Moyo1, Muhammad Wakil Shahzad1, Jonathan G. Terry2, Stewart Smith2, Yoshio Mita3, Yifan Li1

1 Department of Mechanical and Construction Engineering, Faculty of Engineering and Environment, Northumbria University, UK
2 School of Engineering, Institute for Integrated Micro and Nano Systems, The University of Edinburgh, UK
3 Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan

Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.
15:35 [7-3] Damage Assessment Structure of Thermal-Annealing Post-Processing on CMOS LSIs
Yuki Okamoto1, Natsumi Makimoto1, Kei Misumi2, Takeshi Kobayashi1, Yoshio Mita2, Masaaki Ichiki1

1 Sensing System Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan
2 School of Electrical Engineering, The University of Tokyo, Tokyo, Japan

We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the hightemperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with 0.6 um CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the Id-Vg characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575 degree C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.
15:55 [7-4] Improving Performance of FBARs by Advanced Low-Temperature High-Pressure Technology
Yu-Fa Tu1, Ting-Chang Chang2,3, Kuan-Ju Zhou2, Wei-Chun Hung2, Ting-Tzu Kuo4, and Chen-Hsin Lien1

1 Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan
2 Department of Physics, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
3 Center of Crystal Research, National Sun Yat-sen University, Kaohsiung 80424, Taiwan
4 Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan

In this study, a unique supercritical fluid (SCF) treatment is utilized to improve the resonance properties of thin film bulk acoustic resonators (FBARs) composed of a piezoelectric material of AlN. In an etching process of the sacrificial oxide, FBARs suffered from severe surface tension of etching acid solvent, resulting in structural bonding and residues generation. These impact on FABR’s structural integrity would influence its resonance properties. Therefore, a SCF treatment with low surface tension and high penetrability can effectively carry out residues from the release gap in a FBAR, observed from SEM images. The results show that the reflection coefficient, the quality factor, and the effective coupling coefficient are all improved in FABRs.
16:15 [7-5] Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS
Landon Ivy and Amit Lal

The SonicMEMS Laboratory, School of Electrical and Computer Engineering, Cornell University, USA
This work describes a new process for realizing arbitrarily complex polymer structures which feature unique metal patterns on multiple sides. Characterizations were performed to achieve reliable metal covereage, microvia continuity, solderability, and releasability. To showcase this process’ capabilities, three characterization devices, including a functional comb-drive (CD) actuator, will be presented.
18:00 Banquet Chinzanso - Tokyo
18:00 [N/A] Chinzanso - Tokyo
2 Chome-10-8 Sekiguchi, Bunkyo City, Tokyo 112-8680

Day 3 - March 30

09:00 Session 8 Modeling
09:00 [8-1] Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications
Xiaorui Jie, Ronald van Langevelde, Kejun Xia*, Lei Chao, Colin C. McAndrew, Qilin Zhang, Matthew Bacchi, and Wuxia Li

NXP Semiconductors, Front End Innovation
* TSMC, Special Technology Product Engineering
NXP Semiconductors, Business Line Advanced Analog
Accurate modeling of the gate-drain capacitance Cgd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved Cgd model, based on the physics that the drift region under the poly-gate is fully depleted at high Vdg, and validate our model against gate charge measurements for both n- and p-type 90V LDMOS transistors.
09:20 [8-2] Introducing Transfer Learning Framework on Device Modeling by Machine Learning
Kota Niiyama, Hiromitu Awano, and Takashi Sato

Graduate School of Informatics, Kyoto University
In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.
09:40 [8-3] Technology-Dependent Modeling of MOSFET Parasitic Capacitances for Circuit Simulation
Dondee Navarro, Chika Tanaka, Kanna Adachi1, Takeshi Naito, Kenshi Tada and Akira Hokazono

Memory Division, KIOXIA Corporation, Yokohama, Japan
1 Institute of Memory Technology Research and Development, KIOXIA Corporation, Yokohama, Japan
Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance (Cov) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDD junction, which is the physical origin of the Cov bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified.
10:30 Session 9 Novel Materials
10:30 [9-1] Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions
M. Massarotto1, M. Segatto1, F. Driussi1, A. Affanni1, S. Lancaster2, S. Slesazeck2, T. Mikolajick2,3, D. Esseni1

1 DPIA, University of Udine, Udine, Italy
2 NaMLab gGmbH, Dresden, Germany
3 Chair of Nanoelectronics, IHM, TU–Dresden, Germany
Ferroelectric Tunnel Junctions (FTJs) operating as memristors are promising electron devices to realize artificial synapses for neuromorphic computing. But the understanding of their operation requires an in-depth electrical characterization. In this work, an inhouse experimental setup is employed along with novel experimental methodologies to investigate the largesignal (LS) and small-signal (AC) responses of FTJs. For the first time, our experiments and physics-based simulations help to explain the discrepancies between LS and AC experiments reported in previous literature.
10:50 [9-2] Demonstration of frequency doubler application using ZnO–DNTT anti-ambipolar switch device
Yongsu Lee, Hyeon Jun Hwang, and Byoung Hun Lee

Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk 37673, Republic of Korea
This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO–dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) heterojunction structure. The proper combination of n- and p-type thin-film semiconductors achieved a high peak-to-valley ratio of ~10^5 at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO–DNTT AAS device resulted in a high conversion gain of -5 dB and an output frequency purity of 97%.
11:10 [9-3] Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers
Tihomir Knežević1, Lis K. Nanver2

1 Ruđer Bošković Institute, Zagreb, Croatia
2 MESA+ Institute of Nanotechnology, University of Twente, Enschede, The Netherlands
In silicon technology, Schottky diodes mainly exhibit high current levels, and attempts are regularly made to reduce these by introducing 2D layers between the metal contact and the silicon. Defects in such interfacial layers, from weakly bonded structures to actual pinholes, can lead to high, localized metal-semiconductor Schottky currents. Using the example of diodes with an interfacial layer of pure boron (PureB) between an aluminum metallization layer and the Si, a signature for such “nano-Schottky’s” is determined by evaluating the results of several different test-structure arrays and measurement techniques. An adapted bipolar-type measurement is introduced as an additional method to determine whether any high current characteristics originate from a low Schottky barrier height over the entire diode surface or from a localized nano-Schottky structure.